IT6633P datasheet v0.6

IT6633E-P

3-to-1 HDMI 1.3 Active Switch with EDID RAM Preliminary Datasheet

ITE TECH. INC.

General Description

The IT6633 is a three-to-one HDMI v.1.3 active switch that supports a signalling rate of up to 2.25Gbps and the new Deep Color modes. A one-port SINK systems such as flat-panel TVs or LCD projectors could also easily upgrade to three-port by adding an IT6633 at the front. The IT6633 operates in software mode that allows the system to control it via a two-line serial interface, PCSCL/PCSDA. The IT6633 offers two selectable serial programming addresses by PCADR0.

As a active switch, the IT6633 equalizes incoming TMDS data with optimal quality regardless of the incoming signal quality. The highly acclaimed equalization technology of ITE TECH. INC. provides for support of long or low-quality HDMI cables at even the highest speeds. Input terminations of the TMDS inputs and output current levels are both programmable. In addition, the input terminations are disconnectable and hence significantly lower the system power consumption in inactive modes.

The IT6633 embeds an EDID RAM to save the cost of the Three external EDID ROMs. The process of downloading the EDID data into the RAM is simplified by the automatic read-back capability of the

IT6633, minimizing the need of MCU intervention. The IT6633 also embeds three 1K-ohm resisters for HPD signal paths to save external resisters and easy to implement the plug authentication.

The IT6633 also incorporates I2C repeater in its DDC switches, which isolates the DDC capacitances of the two sides of the switch. This allows for longer cable cascading as well as significantly eases the system design to pass Test ID 8-9: DDC/CEC Line Capacitance and Voltage of the HDMI Compliance Test.

The IT6633 also distinguish itself from its peers in that it offers±8kV of Human Body Mode ESD protection to all TMDS high-speed input pins. This saves significant costs in external high-speed ESD diodes, which could be very expensive .

Features

HDMI active switch, providing superior performance over traditional passive switches

Compliant with HDMI 1.3 and DVI 1.0 standards

Serial data rate at up to 2.25Gbps, capable of supporting the following digital video formats in Deep Color Mode at up to 36 bits (12 bits/color):

DTV resolutions: 480i, 576i, 480p, 576p, 720p, 1080i to 1080p

PC resolutions: VGA, SVGA, XGA, SXGA to UXGA

Single 3.3V operation

Internal AC-coupling at TMDS inputs to cope with uneven intra-pair DC levels of incoming TMDS signals.

Embedded EDID RAM saves external EDID ROM costs

Embedded HDP resistors

Integrated HPD switches

Active port detection by monitoring PWR5V inputs and TMDS input clock.

DDC I2C repeater isolates backend DDC capacitive loading from frontend, enhancing the DDC operation compatibility

Human Body Mode ESD protection up to ±8kV for all TMDS differential input pins

Disconnectable input terminations with auto-calibrated impedances

Adaptive input equalization supporting long and short cables at the same time

Software-mode operation providing flexibility

Two possible serial programming device address..

Programmable TMDS output current level

Programmable source terminations compliant with HDMI 1.3 standard, providing optimal source data eyes at high speeds

High-impedance TMDS output when disabled

Optional backend receiver termination detection for auto powerdown

64-Pin LQFP package

RoHS Compliant ( 100% Green available )

Ordering Information

Model Temperature Range Package Type Green/Pb free Option

LQFP Green IT6633E-P 0~70 64-pin

Pin Diagram

16

15

14

CRX2P

NC

33

343536373839404142434445464748CRX2M VCC CRX1P CRX1M VSS CRX0P CRX0M CPWR5V CRXCP CRXCM CSCL CSDA CHPD TXPWR5V

ARXCM ARXCP VCC ARX0M ARX0P VSS ARX1M ARX1P NC ARX2M ARX2P REXT NC ASCL ASDA RESET

Figure 1. IT6633 pin diagram

Pin Description

TMDS High Speed Differential Input Pins (All these pins provide ±8kV HBM ESD Protection)

Pin Name Direction Description Type Pin No. ARX2P Input Channel 2 positive input of Port A TMDS 30 ARX2M Input Channel 2 negative input of Port A TMDS 29 ARX1P Input Channel 1 positive input of Port A TMDS 27 ARX1M Input Channel 1 negative input of Port A TMDS 26 ARX0P Input Channel 0 positive input of Port A TMDS 24 ARX0M Input Channel 0 negative input of Port A TMDS 23 ARXCP Input Clock channel positive input of Port A TMDS 21 ARXCM Input Clock channel negative input of Port A TMDS 20 BRX2P Input Channel 2 positive input of Port B TMDS 14 BRX2M Input Channel 2 negative input of Port B TMDS 13 BRX1P Input Channel 1 positive input of Port B TMDS 11 BRX1M Input Channel 1 negative input of Port B TMDS 10 BRX0P Input Channel 0 positive input of Port B TMDS 8 BRX0M Input Channel 0 negative input of Port B TMDS 7 BRXCP Input Clock channel positive input of Port B TMDS 5 BRXCM Input Clock channel negative input of Port B TMDS 4 CRX2P Input Channel 2 positive input of Port C TMDS 63 CRX2M Input Channel 2 negative input of Port C TMDS 62 CRX1P Input Channel 1 positive input of Port C TMDS 60 CRX1M Input Channel 1 negative input of Port C TMDS 59 CRX0P Input Channel 0 positive input of Port C TMDS 57 CRX0M Input Channel 0 negative input of Port C TMDS 56 CRXCP Input Clock channel positive input of Port C TMDS 54 CRXCM Input Clock channel negative input of Port C TMDS 53

TMDS High Speed Differential Output Pins

Pin Name Direction Description Type Pin No. TX2P Output Channel 2 positive output of output port TMDS 36 TX2M Output Channel 2 negative output of output port TMDS 37 TX1P Output Channel 1 positive output of output port TMDS 39 TX1M Output Channel 1 negative output of output port TMDS 40 TX0P Output Channel 0 positive output of output port TMDS 42 TX0M Output Channel 0 negative output of output port TMDS 43

TXCP Output Clock channel positive output of output port TMDS 45 TXCM Output Clock channel negative output of output port TMDS 46

DDC, HPD and PWR5V Control Pins

Pin Name Direction Description Type Pin No. ASCL I/O Port A DDC bus clock line 5V-Tol. 19 ASDA I/O Port A DDC bus data line 5V-Tol. 18 BSCL I/O Port B DDC bus clock line 5V-Tol. 3 BSDA I/O Port B DDC bus data line 5V-Tol. 2 CSCL I/O Port C DDC bus clock line 5V-Tol. 52 CSDA I/O Port C DDC bus data line 5V-Tol. 51 TXSCL I/O Output Port DDC bus clock line 5V-Tol. 47 TXSDA I/O Output Port DDC bus data line 5V-Tol. 48 TXHPD Input HPD signal of the HDMI Sink 5V-Tol. 44 AHPD Output HPD signal to be sent back to Source connected to Port A LVTTL 16 BHPD Output HPD signal to be sent back to Source connected to Port B LVTTL 1 CHPD Output HPD signal to be sent back to Source connected to Port C LVTTL 50

LVTTL 49 TXPWR5V Output When ‘1’, indicates that the selected input port has a valid

PWR5V input and TMDS clock

APWR5V Input PWR5v of input port A for detection 5V-Tol 15 BPWR5V Input PWR5v of input port B for detection 5V-Tol 6 CPWR5V Input PWR5v of input port C for detection 5V-Tol 55 Other Control and Configuration Pins

Pin Name Direction Description Type Pin No. RESET Input Reset signals for logic blocks (active-high) LVTTL 17 PCSCL Input Serial programming Clock for chip programming (5V-tolerant) Schmitt 34 PCSDA I/O Serial programming Data for chip programming (5V-tolerant) Schmitt 33 PCADR0 Input Control of serial programming device address:

LVTTL 35 ‘0’: 0x94

‘1’: 0x96

(default to ‘0’: 0x94 by internal weak pulled-down resistor of

100kΩ)

REXT Analog External resistor for auto-calibration. Must be tied to VSS via a

Analog 31 500Ω precision resistor.

NC Must be left unconnected 28, 32, 64

Power and Ground Pins

Pin Name Description

Type Pin No. VCC Chip power supply (3.3V) Power 12, 22, 38, 61 VSS

Chip ground

Ground

9, 25, 41, 58

Functional Description

BRX[2,1,0,C]P AHPD BHPD TXSCL/TXSDA TXHPD

PCADR0BRX[2,1,0,C]M

ARX[2,1,0,C]P ARX[2,1,0,C]M

CRX[2,1,0,C]P CRX[2,1,0,C]M

TX[2,1,0,C]P

TX[2,1,0,C]M

CHPD

PCSCL/PCSDA

APWR5V BPWR5V CPWR5V ASCL/ASDA BSCL/BSDA CSCL/CSDA

TXPWR5V

Figure 2. Functional block diagram of IT6633

Power Consumption

Conditions: Typ VCC=3.3V

Operation Supply Current

Mode Condition Current

Typ 180mA

1080P

12 bit

Standby Current

Standby Typ 11.5mA

Power Down Current

Typ 2.5mA

Power

Down

Electrical Specifications

Absolute Maximum Ratings

Symbol Parameter Min. Typ Max Unit

VCC Supply

voltage -0.3 4.0 V

V

voltage -0.3 VCC+0.3

V I Input

V

voltage -0.3 VCC+0.3

V O Output

V IDDC DDC control pins input voltage -0.3 6.0 V

Temperature 125

T J Junction

°C

Temperature -65 150

T STG Storage

°C

V

ESD_HB Human body mode

ARXs, BRXs, CRXs 8000

ESD sensitivity All other pins 2000

ESD_MM Machine mode ESD sensitivity 200 V

Notes:

1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device.

2. Refer to Functional Operation Conditions for normal operation.

Functional Operation Conditions

Symbol Parameter Min. Typ Max Unit

3.3

V

3.465

voltage1 3.135

V CC Supply

25

70

temperature 0

T A Ambient

°C

Θja Junction to ambient thermal resistance 40 °C/W

TMDS Differential Pins

V IDIFF TMDS differential input swing (peak-to-peak) 150 1560 mV

V

3.465

V TERM TMDS output termination voltage1 3.135

3.3

T bit Average bit time of the TMDS data stream 0.444 40 ns

R bit Signaling rate of the serial TMDS data stream 250 2250 Mbps

DDC I/O Pins (ASCL/ASDA, BSCL/BSDA, CSCL/CSDA and TXSCL/TXSDA)

V IDDC DDC input voltage 0 5.5 V

Notes:

1. This is mandated by the HDMI Specifications v1.3 as the supply voltage at pin VCC is also the HDMI termination

voltage.

DC Electrical Specification

Under functional operation conditions Symbol Parameter

Conditions Min.

Typ

Max

Unit

TMDS Differential Output Pins (TX2P/M, TX1P/M, TX0P/M, TXCP/M)

V OHTMDS TMDS output high voltage 3 V CC -10 V CC +10mV V OLTMDS TMDS output low voltage 3 V CC -700 V CC -400

mV

V swing TMDS output single-ended swing 3 R LOAD =50Ω V CC =V TERM =3.3V

400 600 mV

I OFF Single-ended standby output current 3

V OUT =0 10 μA

Logic I/O Pins (LVTTL and Schmitt)

V IH Input high voltage 1 2.0 V

V IL Input low voltage 1 0.8 V V T Switching threshold 1 1.5 V

V OL Output low voltage 1 I OL =2~16mA 0.4 V

V OH Output high voltage 1

I OH =-2~-16mA 2.4 V

V T- Schmitt trigger negative going threshold voltage 1

0.8 1.1 V

V T+ Schmitt trigger positive going threshold voltage 1

1.6

2.0 V

I IN Input leakage current 1

V IN =5.5V or 0 ±5 μA I OZ Tri-state output leakage current 1 V IN =5.5V or 0

±10

μA

I OL

Serial programming output sink current 2

V OUT =0.2V 4 16 mA

Notes:

1. Guaranteed by I/O design.

2. The serial programming output ports are not real open-drain drivers. Sink current is guaranteed by I/O design

under the condition of driving the output pin with 0.2V. In a real serial programming environment, multiple devices and pull-up resistors could be present on the same bus, rendering the effective pull-up resistance much lower than that specified by the I 2C Standard. When set at maximum current, the serial programming output ports of IT6633E are capable of pulling down an effective pull-up resistance as low as 500Ω connected to 5V termination voltage to the standard I 2C V IL . When experiencing insufficient low level problem, try setting the current level to higher than default. Refer to the IT6633E Register Table for proper register setting. 3. Limits defined by HDMI 1.3 standard

Package Dimensions

Figure 3. 64-pin LQFP Package Dimensions