EA218I0BTAV001中文资料
P R E L I M I N A R Y I N F O R M A T I O N
? 1998 Zarlink Semiconductor, Inc.1Rev. 2.1- February, 1999
Distinctive Characteristics
8 independent Ethernet Access Ports 9
Two 10/100Mbps Fast Ethernet Ports
z Direct interface with 10BaseT
transceiver z IEEE 802.3u compliant MII
(Media Independent Inter-face) and Serial Management interface z Direct interface with
100BaseTX, T2, T4, or TF transceivers 9
Six 10Mbps Ethernet Ports z Direct interface with 10BaseT
transceiver
0.5 micron 3.3 Volt CMOS process 352-BGA package Operating frequency 9-3333 MHz maximum 9-4040 MHz maximum 9-50
50 MHz maximum
9
-66 66.66 MHz maxi-mum
32-bit Local Buffer Memory Interface 9Supports 128k to 1M bytes 9
Utilize high performance 32-bit Synchronous Burst SRAM
Hardware assisted Buffer and Queue Management 16-bit Management Bus I/O Interface 9Allows host to access Control Registers & Local Buffer Memory 9Big and Little Endian CPUs 9
Direct interface to standard micro-processors, including 386, 486families and Motorola MPC series embedded processors 32-bit XpressFlow Bus Interface 9
Uses Granule for frame transfer-ring between Access Controllers
Unicast, multicast, and broadcast frames 9
Also detects IEEE 802.3X MAC Control frames
EA218 – 6+2 Ports Ethernet Access Controller
XpressFlow 2020Ethernet Routing Switch Chipset
Block Diagram-EA218 6+2 Ports Ethernet Access Controller
General Description
The EA-208 provides the Ethernet network access interface. It supports 6 ports of 10Mbps Ethernet and 2 ports of 10/100 Mbps Ethernet. The 10Mbps ports uses serial interface to con-nect with external 10BaseT or other 10Mbps PHY devices. For 10/100 Mbps ports, MII inter-face is used to connect external PHY devices.
The EA-208 provides the MAC protocols, handles the local buffer memory interface and man-agement, arbitrates among multiple priority queues, and interfaces with the XpressFlow Engine and other Access Controllers through the XpressFlow message passing protocol.
Related Components:
SC220– XpressFlow Engine
EA218E–8-port 10Mb Ethernet Access Controller EA234– 4-port 10/100Mbps Ethernet Access Controller
Characteristics Continue
Works together with SC-220 Xpress-Flow Engine Forwards frames at full line-rate
9
Distributed Flow Caching? to re-duce frame forwarding latency
Half and Full Duplex operation Programmable Flow Control 9Jam Collision for Half Duplex Mode
9
Transmit Flow Control Frame for IEEE 802.3x Full Duplex Mode
Supports Store-&-Forward frame for-warding mode Multi-Media ready with QoS supports 9
Four frame transmission priority queues
Complies with IEEE 802.1 Bridge Standard 9
Assigns one unique MAC Address for each port
VLAN ID Tagging & Stripping 9
Auto padding if necessary after stripping Automatic retry frame transmission 9Transmit collision 9
Transmit buffer under-run
Automatic receive filtering for bad frames for Store & Forward Mode 9Bad FCS
9Short events or frames under 64bytes
9
Long events or frames over 1518/1522 bytes
Automatic statistic collection for RMON
Block Diagram –
EA218E 8-Port Ethernet Access Controller
Typical Application :
9 A 22-port Ethernet Switch with 2-Fast Ethernet
System Block Diagram --22-Ports Ethernet Switch with 2 Fast Ethernet Up-Links
1.PIN ASSIGNMENT
1.1Logic Symbol
TEST M_MDC M_MDIO
P_CS#P_ADS#P_RWC P_BS16#P_RDY#P_INT P_RST#P_CLK P_A[11:1]Mm_RXD[3:0]Mm_RXDV
Mm_RXC
Mm_RXER Mm_TXER Mm_TXC Mm_TXEN Mm_TXD[0]Mm_TXD[1]Mm_TXD[2]Mm_TXD[3]Mm_COL Mm_CRS Mm_LNK
Tm_RXD Tm_RXC Tm_TXC Tm_TXEN Tm_TXD Tm_LPBK Tm_FD Tm_COL Tm_CRS Tm_LNK
Tm_RXD Tm_RXC Tm_TXC Tm_TXEN Tm_TXD Tm_LPBK Tm_FD Tm_COL Tm_CRS Tm_LNK
MII Mode
10BaseT Serial Xface
L_CLK S_IRDY S_TABT#S_REQ#S_GNT#
S_CLK
1.2Pin Assignment (Preliminary)
Note:#Active low signal
Input Input signal
In-ST Input signal with Schmitt-Trigger
Output Output signal (Tri-State driver)
Out-OD Output signal with Open-Drain driver
I/O-TS Input & Output signal with Tri-State driver
I/O-OD Input & Output signal with Open-Drain driver
5VT Input with 5V Tolerance
Output signal with programmable polarity.
Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
These pins are reserved for internal use only. They should be left unconnected.
Pin No(s).Symbol Type
Max
I OL/ I OH Name and Functions
Management Bus Interface
J25,K26,L24,K25,L26,
M24,L25,M26,N24,M25,
P24,N26,N25,R24,P26, P25
P_D[15:0]TTL I/O-TS (5VT)16mA Management Bus – Data Bit [15:0]
C26,D24,C25,E24,D26,
D25,F24,E26,E25,G24, F26
P_A[11:1]TTL In (5VT)Management Bus – Address Bit [11:1] F25P_ADS#TTL In (5VT)Management Bus – Address Strobe
H25P_RWC TTL In (5VT)Management Bus – Read/Write Control J24P_RDY#TTL Out-OD16mA Management Bus – Data Ready
G25P_BS16#TTL Out-OD16mA Management Bus – 16 bit Data Bus
G26P_CS#TTL In (5VT)Management Bus – Chip Select
H26P_INT CMOS Output4mA Management Bus – Interrupt Request J26P_RST#TTL In-ST (5VT)Management Bus – Master Reset
K24P_CLK TTL In (5VT)Management Bus – Bus Clock XpressFlow Bus Interface
C23,A23,B22,C22,A22S_D[31:27] /
P_C[0:4]CMOS I/O-TS12mA XpressFlow Bus – Data Bit [31:27] or Manage-
ment Bus Interface Configuration bit [0:4]
B21,D20,C21,A21,B20,
A20,C20,B19,A19,C19,
B18,A18,B17,C18,A17,
D17,B16,C17,A16,B15,
A15,C16,B14,D15,A14,
C15,B13
S_D[26:0]CMOS I/O-TS12mA XpressFlow Bus – Data Bit [26:0]
B12S_MSGEN#CMOS I/O-TS12mA XpressFlow Bus – Message Envelope
A12S_EOF#CMOS I/O-TS12mA XpressFlow Bus – End of Frame
C14S_IRDY CMOS I/O-TS12mA XpressFlow Bus – Initiator Ready
C13S_TABT#CMOS I/O-OD12mA XpressFlow Bus – Target Abort
B23S_HPREQ#CMOS I/O-OD12mA XpressFlow Bus – High Priority Request A24S_REQ#CMOS Output4mA XpressFlow Bus – Bus Request to SC201 B24S_GNT#CMOS Input XpressFlow Bus – Bus Grant from SC201 A13S_OVLD#CMOS Input XpressFlow Bus – Bus Overload
D13S_CLK CMOS Input XpressFlow Bus – Clock
Pin No(s).Symbol Type Name and Functions
Control Buffer Memory Interface
M4,N2,L3,M1,M2,L1,K3,
L2,K4,K1,J3,K2,J1,J2,
H3,H1,H2,G3,G1,G2,F1,F3,F
2,E1,E3,E2,D1,D3,D2,C1,C2,
B1
L_D[31:0]TTL I/O-TS 8mA Local Memory Bus – Data Bit [31:0]
A6,B6,C8,A7,D8,D7,C9,
A8,B8,A9,C10,B9,D10,
A10,C11,B10,A11
L_A[18:2]CMOS Output8mA Local Memory Bus – Address Bit [17:2]
C7L_A[19] /
L_OE[3]#CMOS Output8mA Local Memory Bus – Address Bit [19] or Memory
Read Chip Select [3]
D5,A5,A3L_OE[2:0]#CMOS Output2mA Local Memory Read Chip Select [2:0]
D7,E4,B5,C4L_WE[3:0]#CMOS Output2mA Local Memory Write Chip Select [3:0]
C6,B4,A4,C5L_BWE[3:0]#CMOS Output8mA Local Memory Byte Write Enable, Byte [3:0] B3L_ADSC#CMOS Output8mA Local Memory Controller Address Status
G4L_CLK CMOS Output8mA Local Memory Clock input
Ethernet Access Port cont. [7:0]
AF20,AE17,AD12,AD9, AC2,T25T[7:2]_RXD TTL In (5VT) Receive Data – (one for each 10Mbps Serial In-
terface Port)
AC25,AF6T[1:0]_RXD TTL In (5VT)
AD19,AD16,AE14,AF10,AC2 1U24T[7:2]_RXC TTL In (5VT) Receive Clock – (one for each 10Mbps Serial In-
terface Port)
AC24,AE7T[1:0]_RXC TTL In (5VT)
AF18,AD14,AE12,AF8, W2,AA25,AE22,AD1T[7:0]_TXC TTL In (5VT)Transmit Clock – (one for each 10Mbps Serial In-
terface Port)
AE19,AF15,AF12,AD8, W1,AA24T[7:2]_TXEN CMOS Out 4mA Transmit Enable – (one for each 10Mbps Serial
Interface Port)
AF22,AF2T[1:0]_TXEN CMOS Output
AE20,AF16,AF13,AE10, Y1,W25T[7:2]_TXD CMOS Out 4mA Transmit Data – (one for each 10Mbps Serial In-
terface Port)
AF23,AE4T[1:0]_TXD CMOS Output
AD18,AD15,AE13,AF9, Y2,Y26T[7:2]_LPBK CMOS Out 2mA Loop Back Enable – (one for each 10Mbps Serial
Interface Port)
AE23,AF3T[1:0]_LPBK CMOS Output
AF19,AE16,AD11,AE9, V3,AA26T[7:2]_FD CMOS Out 2mA Full Duplex Mode – (one for each 10Mbps Serial
Interface Port)
AD21,AE3T[1:0]_FD CMOS Output
AD17,AE15,AF11,AE8, V1,AB26T[7:2]_COL TTL In (5VT) Collision Detected – (one for each 10Mbps Serial
Interface Port)
AD20,AC23T[1:0]_COL TTL In (5VT)
AE18,AD13,AD10,AD7, U3,AB24,T[7:2]_CRS TTL In (5VT) Carrier Sense – (one for each 10Mbps Serial In-
terface Port)
AF21,AD2T[1:0]_CRS TTL In (5VT)
AF17,AF14,AE11,AF7, V2,AB25,T[7:2]_LNK TTL In (5VT) Link Status – (one for each 10Mbps Serial Inter-
face Port)
AE21,AB3T[1:0]_LNK TTL In (5VT)
Pin No(s).Symbol Type
Max
I OL/ I OH Name & Functions
Test Facility
A25T_MODE CMOS I/O-TS 2mA Test Pin – Set Test Mode upon Reset, and pro-
vides test status output during test mode
N1,M3,P2,P1,N3,R2,P3,R1,T
2R3,T1,R4,U2,T3,U1,U4
T_D[15:10] CMOS Output4mA Test Pins – Reserved for internal use only
Pin No(s).Symbol Type Name & Functions
Power Pins
D6,D11,D16,D21,F4,
F23,L4,L23,T4,T23,AA4,AA23
AC6,AC11,AC16,AC21
VDD Power+3.3 Volt DC Supply
A1,A2,A26,B2,B25,B26,
C3,C24,D4,D9,D14,D19,D23,
H4,J23,N4,P23,V4,W23,AC4,
AC8,AC13,
AC18,AC23,AD3,AD24,
AE1,AE2,AE25,AF1, AF25
VSS Power Ground
1.3Pin Reference Table: (352 pin BGA)
Pin #Signal Name Pin #Signal Name Pin #Signal Name Pin #Signal Name Pin #Signal Name
F26P_A[1]C18S_D[13]E3L_D[7] V1T3_COL T2T_D[7] G24P_A[2]B17S_D[14]E1L_D[8] V3T3_FD R1T_D[8] E25P_A[3]A18S_D[15]F2L_D[9] Y2T3_LPBK P3T_D[9] E26P_A[4]B18S_D[16]F3L_D[10] Y1T3_TXD R2T_D[10] F24P_A[5]C19S_D[17]F1L_D[11] W1T3_TXEN N3T_D[11] D25P_A[6]A19S_D[18]G2L_D[12] W2T3_TXC P1T_D[12] D26P_A[7]B19S_D[19]G1L_D[13] AC1T3_RXC P2T_D[13] E24P_A[8]C20S_D[20]G3L_D[14] AC2T3_RXD M3T_D[14] C25P_A[9]A20S_D[21]H2L_D[15] AF7T4_LNK N1T_D[15] D24P_A[10]B20S_D[22]H1L_D[16] AD7T4_CRS
C26P_A[11]A21S_D[23]H3L_D[17] AE8T4_COL D6VDD
F25P_ADS#C21S_D[24]J2L_D[18] AE9T4_FD D11VDD
G26P_CS#D20S_D[25]J1L_D[19] AF9T4_LPBK D16VDD
H25P_RWC B21S_D[26]K2L_D[20] AE10T4_TXD D21VDD
G25P_BS16#A22S_D[27] / P_C[4]J3L_D[21] AD8T4_TXEN F4VDD
J24P_RDY#C22S_D[28] / P_C[3]K1L_D[22] AF8T4_TXC F23VDD
J26P_RST#B22S_D[29] / P_C[2]K4L_D[23] AF10T4_RXC L4VDD
H26P_INT A23S_D[30] / P_C[1]L2L_D[24] AD9T4_RXD L23VDD
K24P_CLK C23S_D[31] / P_C[0]K3L_D[25] AE11T5_LNK T4VDD
P25P_D[0]L1L_D[26] AD10T5_CRS T23VDD
P26P_D[1]A11L_A[2]M2L_D[27] AF11T5_COL AA4VDD
R24P_D[2]B10L_A[3]M1L_D[28] AD11T5_FD AA23VDD
N25P_D[3]C11L_A[4]L3L_D[29] AE13T5_LPBK AC6VDD
N26P_D[4]A10L_A[5]N2L_D[30] AF13T5_TXD AC11VDD
P24P_D[5]D10L_A[6]M4L_D[31] AF12T5_TXEN AC16VDD
M25P_D[6]B9L_A[7]AE12T5_TXC AC21VDD
N24P_D[7]C10L_A[8]AB3T0_LNK AE14T5_RXC A1GND
M26P_D[8]A9L_A[9]AD2T0_CRS AD12T5_RXD A2GND
L25P_D[9]B8L_A[10]AC3T0_COL AF14T6_LNK A26GND
M24P_D[10]A8L_A[11]AE3T0_FD AD13T6_CRS B2GND
L26P_D[11]C9L_A[12]AF3T0_LPBK AE15T6_COL B25GND
K25P_D[12]B7L_A[13]AE4T0_TXD AE16T6_FD B26GND
L24P_D[13]D8L_A[14]AF2T0_TXEN AD15T6_LPBK C3GND
K26P_D[14]A7L_A[15]AD1T0_TXC AF16T6_TXD C24GND
J25P_D[15]C8L_A[16]AE7T0_RXC AF15T6_TXEN D4GND
B6L_A[17]AF6T0_RXD AD14T6_TXC D9GND
D13S_CLK A6L_A[18]AE21T1_LNK AD16T6_RXC D14GND
A13S_OVLD#C7L_A[19] / OE[3]#AF21T1_CRS AE17T6_RXD D19GND
B23S_HPREQ#D5L_OE[2]#AD20T1_COL AF17T7_LNK D23GND
A24S_REQ#A5L_OE[1]#AD21T1_FD AE18T7_CRS H4GND
B24S_GNT#A3L_OE[0]AE23T1_LPBK AD17T7_COL J23GND
B12S_MSGEN#D7L_WE[3]#AF23T1_TXD AF19T7_FD N4GND
A12S_EOF#E4L_WE[2]#AF22T1_TXEN AD18T7_LPBK P23GND
C14S_IRDY B5L_WE[1]#AE22T1_TXC AE20T7_TXD V4GND
C13S_TABT#C4L_WE[0]#AC24T1_RXC AE19T7_TXEN W23GND
B13S_D[0]C6L_BWE[3]#AC25T1_RXD AF18T7_TXC AC4GND
C15S_D[1]B4L_BWE[2]#AB25T2_LNK AD19T7_RXC AC8GND
A14S_D[2]A4L_BWE[1]#AB24T2_CRS AF20T7_RXD AC13GND
D15S_D[3]C5L_BWE[0]#AB26T2_COL AC18GND
B14S_D[4]B3L_ADSC#AA26T2_FD A25T_MODE AC23GND
C16S_D[5]G4L_CLK Y26T2_LPBK AD3GND
A15S_D[6]B1L_D[0] W25T2_TXD U4T_D[0] AD24GND
B15S_D[7]C2L_D[1] AA24T2_TXEN U1T_D[1] AE1GND
A16S_D[8]C1L_D[2] AA25T2_TXC T3T_D[2] AE2GND
C17S_D[9]D2L_D[3] U24T2_RXC U2T_D[3] AE25GND
B16S_D[10]D3L_D[4] T25T2_RXD R4T_D[4] AF1GND
D17S_D[11]D1L_D[5] V2T3_LNK T1T_D[5] AF25GND
A17S_D[12]E2L_D[6] U3T3_CRS R3T_D[6]
Note: Output signals with programmable polarity.
Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
These pins are reserved for internal use only. They should be left unconnected.
2.FUNCTIONAL DESCRIPTION
2.1Local Memory (Local Buffer Memory) Interface
Uses industry standard Synchronous Burst Mode SRAM up to 1M bytes
932k x 32, 64k x 32, 128k x 32, or 256k x 32
Provides separate Read and Write Chip Selects ( L_OE[3:0]# and L_WE[3:0]# ) for each memory chip
Supports back to back Read or Write operations across memory chips
2.1.1Pin Description
Symbol Type Name and Functions
L_D[31:0] TTL I/O-TS Local Memory Data Bus Bit [31:0]– a 32-bit synchronous data bus.
L_A[18:2]CMOS Output Local Memory Address Bus Bit [18:2] – Bit [18:2] of a synchronous address bus. The
memory address is sampled when L_CS# is enabled and L_ADSC# is asserted.
L_A[19] / L_OE[3]#CMOS Output Local Memory Address Bus Bit [19] or Local Memory Read Chip Select [3]– De-pends on memory configuration, this pin can be used as the Local Memory Address Bit
[19] or as the Local Memory Read Chip Select [3].
L_OE[2:0]#CMOS Output Local Memory Read Chip Select [2:0] – allows up to read one of the 4 banks of mem-
ory.
L_WE[3:0]#CMOS Output Local Memory Write Chip Select [3:0]– allows up to write one of the 4 banks of mem-
ory.
L_BWE[3:0]#CMOS Output Local Memory Byte Write Enable [3:0]– use to write individual bytes.
L_ADSC#CMOS Output Local Memory Controller Address Status– to load a new address.
L_CLK CMOS Output Local Memory Clock– a synchronous clock to memory devices.
L_D[31:0]TTL I/O-TS Local Memory Data Bus Bit [31:0]– a 32-bit synchronous data bus.
L_A[18:2]CMOS Output Local Memory Address Bus Bit [18:2]– Bit [17:2] of a synchronous address bus. The
memory address is sampled when L_CS# is enabled and L_ADSC# is asserted.
L_A[19] / L_WE[3]#CMOS Output Local Memory Address Bus Bit [19] or Local Memory Write Chip Select [3]– De-pends on memory configuration, this pin can be used as the Local Memory Address Bit
[19] or as the Local Memory Write Chip Select [3].
L_WE[2:0]#CMOS Output Local Memory Write Chip Select [2:0]– allows up to write one of the 4 banks of mem-
ory.
L_OE[3:0]#CMOS Output Local Memory Read Chip Select [3:0]– allows up to read one of the 4 banks of mem-
ory.
L_BWE[3:0]#CMOS Output Local Memory Byte Write Enable [3:0]– use to write individual bytes.
L_ADSC#CMOS Output Local Memory Controller Address Status– to load a new address.
L_CLK CMOS Output Local Memory Clock– a synchronous clock to memory devices.
Note: These pins have weak internal pull up resistors (50k to 100k Ohms each).
2.1.2Supported Memory Configurations
Read/Write Chip Select and High Address Bits
Chip #3
Chip #2
Chip #1
Chip #0
RAM Chip Size # of RAM Chips Total Buffer
Memory Size L_WE[3]#L_A[19] /L_OE[3]#L_WE[2]#L_OE[2]#L_WE[1]#L_OE[1]#L_WE[0]#L_OE[0]#
32k x 32
1128k bytes ------------------------L_WE[0]#L_OE[0]#
2256k bytes ----------------L_WE[1]#L_OE[1]#L_WE[0]#L_OE[0]#4
512k bytes L_WE[3]#L_OE[3]#L_WE[2]#L_OE[2]#L_WE[1]#L_OE[1]#L_WE[0]#L_OE[0]#
64k x 32
1256k bytes ------------------------L_WE[0]#L_OE[0]#
2512k bytes ----------------L_WE[1]#L_OE[1]#L_WE[0]#L_OE[0]#4
1M bytes L_WE[3]#L_OE[3]#L_WE[2]#L_OE[2]#L_WE[1]#L_OE[1]#L_WE[0]#L_OE[0]#
128k x321512k bytes ------------------------L_WE[0]#L_OE[0]#21M bytes ----------------L_WE[1]#L_OE[1]#L_WE[0]#L_OE[0]#
256k x32
1
1M bytes
----L_A[19]
----------------L_WE[0]#L_OE[0]#
2.1.3
Bus Cycle Waveforms
L_CLK L_ADSC#L_CS#L_A[19:2]L_WE[3:0]#L_BWE[3:0]#L_OE[3:0]#
L_D[31:0] (Wr)
L_D[31:0] (Rd)
Typical Local Memory Access Operations
2.2Processor Bus Interface
Supports various industry standard micro-processors including: 9Intel 186, 386, and 486 family or equivalent
9Motorola MPC series embedded processors
Easily adapts to other industry standard CPUs
Provides separate Address and Data bus
Supports Big & Little Endian byte ordering Supports 16-bit Data Bus
Supports early RDY cycle
9Meets timing requirement for Intel/AMD 186 family proc-essors
Supports 1X or 2X CPU Clock
92X CPU Clock for 386 family processors
Provides a single interrupt signal to Switch Manager CPU
2.2.1Pin Description
Symbol Type Name and Functions
P_C[4:0]CMOS Input Processor Configuration bit [4:0]:– During the Reset Cycle, the P_C[4:0] pins provides the
processor configuration. By using external weak pull-up or -down resistors, they define the Ex-
ternal Management Bus Interface Configuration. These inputs are sampled at the trailing edge of
the Reset cycle.
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Bus width – For EA-208, it is default to 16-bit CPU Bus interface, and
the setting of this bit is ignored.
C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid. If C[4] is High,
the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4]
is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are
valid.
C[0]C[1]C[2]C[3]C[4]
CPU Clock Byte Order RWC Bus Size RDY Timing
Lo1X Clock Little Endian P_R/W#n/a Normal
Hi2x Clock Big Endian P_W/R#n/a Early
After RESET, these pins are used as XpressFlow Bus Data bit [31:27].
P_A[11:1]TTL In (5VT)Address Bus Bit [11:1]– I/O port address
P_D[15:0]TTL I/O-TS (5VT)Data Bus Bit [15:0]– a 16-bit synchronous data bus.
P_ADS#TTL In (5VT)Address Strobe– indicates valid address is on the bus
P_RWC TTL Input (5VT)Read/Write Control– indicates the current bus cycle is a read or write cycle.C[1] defines the
polarity of this signal during the Reset cycle.
C[1]=Low P_R/W# is used for PowerPC or other similar processors.
C[1]=High P_W/R# is used for 386, 486 or other similar processors P_RDY#TTL Out-OD Data Ready– timing indicates for bus data valid
P_BS16#TTL Out-OD Bus Size 16– response to bus master that the EA208 only supports 16-bit data bus width.
P_CS#TTL Input (5VT)Chip Select– indicates the XpressFlow Engine is the target for the current bus operation.
P_INT CMOS Output Interrupt Request to Switch Manager CPU The polarity of this signal output is programmable
via chip configuration register.
P_RST#TTL In-ST (5VT)CPU Reset– Synchronous reset Input from Switch Manager CPU
P_CLK TTL In (5VT)CPU Clock– 2X Clock for 386 family, and 1X Clock for the others
2.2.2
Motorola MPC801 Processor Interface
P_CLK {CLKOUT}P_ADS#{TS#}P_A[11:1]{A[20:30]}P_CS#P_RWC {RD/WR#}P_RDY#{TA#}P_D[15:0]{D[0:15]}P_D[15:0]
{D[0:15]}(out)
(in)Note:Mnemonics with in {} are the equivalent signals defined by MPC801
Typical Motorola MPC801 CPU I/O Access Operations
2.2.3
Intel 486 Processor Interface
P_CLK P_ADS#P_A[11:1]P_CS#P_W/R#P_RDY#P_D[15:0] (in)
P_D[15:0] (out)
Typical 486 CPU I/O Access Operations
2.2.4
Intel 386 Processor Interface
P_CLK
PH2 (internal)
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[15:0] (in)
P_D15:0] (out)
Typical 386 CPU I/O Access Operations
P_CLK
PH2 (internal)
P_RST#
Internal PH2 Clock Synchronization **
Note:** See Intel 386 Processor Data Book for more details
2.2.5Register Map
Note:All 32-bit registers are D-word aligned.
All 16-bit registers are also D-word aligned and right justified.
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
This is a Global Register. CPU is allowed to write the Global Register of all devices by a single operation.
These registers are reserved for system diagnostic usage only.
I/O Offset
Register Description Little
Endian
Big
Endian
Reg.
Size
W/R Note:
Device Configuration Registers (DCR)
GCR Global Control Register hF00hF0216-bit W/-- DCR0Device Status Register hF00hF0216-bit--/R
DCR1Signature & Revision Register hF10hF1216-bit--/R
DCR2ID Register hF20hF2216-bit W/R
DCR3Device Configuration Register hF30hF3216-bit W/R
DCR4Interfaces Status Register hF40hF4216-bit--/R
DTSR Test Register hF70hF7216-bit W/R Interrupt Controls
ISR Interrupt Status Register – Unmasked hF80hF8216-bit--/R
ISRM Interrupt Status Register – Masked hF90hF9216-bit--/R
IMSK Interrupt Mask Register hFA0hFA216-bit W/R
IAR Interrupt Acknowledgment Register hFB0hFB216-bit W/--
Buffer Memory Interface
MWAR Memory Write Address Reg. – Single Cycle hE08hE0832-bit W/R
MRAR Memory Read Address Reg. – Single Cycle hE18hE1832-bit W/R
MBAR Memory Address Register – Burst Mode hE28hE2832-bit W/R MWBS Memory Write Burst Size (in D-words)hE40hE4216-bit W/R
MRBS Memory Read Burst Size (in D-words)hE50hE5216-bit W/R MWDR Memory Write Data Register hE68hE6832-bit W/--MWDX Memory Write Data Reg. – Byte Swapping hE6C hE6C32-bit W/--
MRDR Memory Read Data Register hE68hE6832-bit--/R
MRDX Memory Read Data Reg. – Byte Swapping hE6C hE6C32-bit--/R
FCB Buffer & Stack Management
FCBBA Frame Control Buffer – Base Address hD00hD0216-bit W/R FCBAG Frame Control Buffer – Buffer Aging Status hD30hD3216-bit--/R FCBSL Frame Ctrl Buffer Stack – Size Limit hD90hD9216-bit W/R FCBST Frame Ctrl Buffer Stack – Buffer Low Threshold hDA0hDA216-bit W/R FCBSS Frame Ctrl Buffer Stack – Allocation Status hDB0hDB216-bit--/R
I/O Offset
Register Description Little
Endian
Big
Endian
Reg.
Size
W/R Note:
Access Control Function (Chip Level controls)
AVXR VLAN Control Table (VCT) Index Register hC00hC0216-bit W/--
AVDR VCT Data Register hC10hC1216-bit W/R
AVTC VLAN Type Code hC20hC2216-bit W/R
AXSC Transmission Scheduling Control Register hC30hC3216-bit W/R
AMIIC MII Command Register hC40hC4032-bit W/--
AMIIS MII Status Register hC40hC4032-bit--/R
AFCR Flow Control Register hC70hC7216-bit W/R
AMAR0Multicast Address. for MAC Control Frames Byte [1,0]hC80hC8216-bit W/R
AMAR1Byte [3,2]hC90hC9216-bit W/R
AMAR2Byte [5,4]hCA0hCA216-bit W/R
AMCT MAC Control FrameType Code Register hCB0hCB216-bit W/R
ADAR0Base MAC Address Register – Byte [1,0]hCC0hCC216-bit W/R
ADAR1Base MAC Address Register – Byte [3,2]hCD0hCD216-bit W/R
ADAR2Base MAC Address Register – Byte [5,4]hCE0hCE216-bit W/R Ethernet MAC Port Control Registers – (substitute [n] with Port Number, n = {0..3] )
ECR0MAC Port Control Register h n00h n0216-bit W/R
ECR1MAC Port Configuration Register h n10h n1216-bit W/R
ECR2MAC Port Interrupt Mask Register hn20hn2216-bit W/R
ECR3MAC Port Interrupt Status Register hn30hn3216-bit--/R EXSR MAC Tx Status Register hn40hn4216-bit--/R EXEC MAC Tx Error Counters hn50hn5216-bit--/R ERSR MAC Rx Status Register hn68hn6832-bit--/R EREC MAC Rx Error Counters hn78hn7832-bit--/R
2.3XpressFlow Bus Operation
Zarlink’s optimized XpressFlow Bus architecture
Provides 1.6G bps switching bandwidth
9-33 1.07G bps
9-40 1.28G bps
9-50 1.6G bps
Full multi bus master structure
Allows XpressFlow Engine to communicate with Access Con-trollers via a message passing protocol
9Command Messages for passing control information be-tween devices
9Data Messages for forwarding an Ethernet frame from re-ceiving port to transmission port
Built-in intelligent bus load regulator for data traffic balancing Provides centralized bus arbitration with two level request pri-
orities
9High priority for Data Messages
9Low priority for Command Messages
2.3.1Pin Description
Symbol Type Name and Functions
S_D[31:0]CMOS
I/O-TS Data Bus Bit [31:0]– a 32-bit synchronous data bus.
Note:During the system RESET period, Data Bit [31:28] are used as Processor Interface Configuration bit [0:3]
S_MSGEN#CMOS
I/O-TS Message Envelope– encompasses the entire period of a message transfer. Targets use the leading edge of this signal to detect the beginning of a message transfer, and to decode the message header for the intended target(s).
S_EOF#CMOS
I/O-TS End of Frame– only used by frame data transfer messages to identify the end of frame condi-tion. This signal is synchronous with the Rx Frame Status word appended to the end of the message.
S_IRDY CMOS
I/O-TS Initiator Ready– a normal true signal. When negated, it indicates the initiator had asserted wait state(s) in between command words. Target should use this signal as enable signal for latching the data from the bus.
S_TABT#CMOS
I/O-OD Target Abort– when asserted, the target had aborted the reception of current message on the bus.
S_HPREQ#CMOS
I/O-OD High Priority Request– indicates one or more Bus Requester is requesting for high priority message transfer.
S_REQ#CMOS
Output Bus Request–Bus Request signals from Access Controller to Bus Access Arbitrator in Xpress-Flow Engine
S_GNT#CMOS In-
put
Bus Grant–Bus Grant signals from Bus Arbitrator to Bus Requester
S_OVLD#CMOS
Output Bus Overload– when asserted, all data forwarding bus bandwidth has been allocated. Cannot support additional load for data forwarding traffic.
S_CLK CMOS
Input
XpressFlow Bus Clock– 33MHz system clock
2.3.2
Bus Cycle Waveforms
S_CLK
S_MSGEN#
S_D[31:0]
S_EOF#
S_IRDY
XpressFlow Bus Data Transfer Cycle
Command Cycle Data Xfer w/o Data Aborted Command
S_CLK
S_MSGEN#
S_D[31:0]
S_EOF#
S_TABT#
Other XpressFlow Bus Cycles
S_CLK S_REQ[k]#S_REQ[j]#S_HPREQ#
High Priority Request pre-empts the low priority request.
S_MSGEN#
S_REQ[j]#
S_GNT[j]#
S_HPREQ#
S_REQ[I]#
S_GNT[I]#
XpressFlow Bus arbitration
S_CLK
S_OVLD#
Bus Overload pre-empts the data transfer request
2.410Mb Serial Interface for Port 0 through 7
Fully compliant with IEEE 802.3 10M bit Serial Interface Stan-dard for connecting with external 10Mbps Ethernet Physical Layer Transceiver
Supports 10Mbps 10BaseT serial interface Supports both half and full duplex operation
2.4.1Pin Description
Symbol Type Name and Functions
Tn_RXD TTL In (5VT)Receive Data – (one for each 10M bit Serial Interface Port) a receive data stream.
Tn_RXC TTL In (5VT)Receive Clock – (one for each 10M bit Serial Interface Port) from external phy for sampling the receive data from Tn_RXD input
Tn_TXC TTL In (5VT)Transmit Clock – (one for each 10M bit Serial Interface Port) a continuous clock input with 35% to 65% duty cycles.
Tn_TXEN CMOS Output Transmit Enable – (one for each 10M bit Serial Interface Port)
Tn_TXD CMOS Output Transmit Data – (one for each 10M bit Serial Interface Port) a transmit data stream.Tn_LPBK CMOS Output Loop Back Enable – (one for each 10M bit Serial Interface Port) The polarity of this signal is programmable via Port Configuration Register
Tn_FD
CMOS Output Full Duplex Mode – (one for each 10M bit Serial Interface Port) The polarity of this signal is programmable via Port Configuration Register
Tn_COL TTL In (5VT)Collision Detected – (one for each 10M bit Serial Interface Port)Tn_CRS TTL In (5VT)Carrier Sense – (one for each 10M bit Serial Interface Port)
Tn_LNK
TTL In (5VT)
Link Status –(one for each 10M bit Serial Interface Port) The polarity of this signal is pro-grammable via Port Configuration Register
Note :
“n” is the port number [7:0]
These signals have programmable output polarity.
TXC
TXEN
TXD
10M bit Serial Interface – Transmit Timing
CRS
RXC
RXD
10M bit Serial Interface – Receive Timing
2.5Test Pins
Symbol Type Name and Functions
T_MODE
CMOS I/O-TS
Test Mode Selection & Test Output – Set Test Mode upon Reset, and provides test status output during test mode
3.DC SPECIFICATION
3.1ABSOLUTE MAXIMUM RATINGS
Storage Temperature-50°C to +125°C
Operating Temperature0°C to +70°C
Supply Voltage V DD with Respect to V SS+3.0 V to +3.6 V
Voltage on 5V Tolerant Input Pins-0.5 V to (V DD+ 1.8 V)
Voltage on Other Input Pins-0.5 V to (V DD + 10%)
Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Ab-solute Maximum Ratings for extended periods may affect device reliability.
3.2DC CHARACTERISTICS
V DD= +3.0 V to +3.6 V T AMBIENT= 0°C to +70°C
Preliminary
Symbol Parameter Description Min Typ Max Unit
f osc Frequency of Operation (-40)2040.0000MHz
Frequency of Operation (-50)2050.0000MHz
Frequency of Operation (-66)2066.6667MHz
I DD Supply Power – @ 40 MHz (V DD=3.3 V)300500mA
Supply Power – @ 50 MHz (V DD=3.3 V)300500mA
Supply Power – @ 66.67 MHz (V DD=3.3 V)300500mA V OH-CMOS Output High Voltage (CMOS) I OH= maximum V DD- 0.5V V OL-CMOS Output Low Voltage (CMOS) I OL= maximum0.45V V OH-TTL Output High Voltage (TTL) I OH= maximum 2.4V V OL-TTL Output Low Voltage (TTL) I OL= maximum0.45V V IH-CMOS Input High Voltage (CMOS)VDD x 70%V DD+ 10%V V IL-CMOS Input Low Voltage (CMOS)-0.5VDD x 30%V V IH-TTL Input High Voltage (TTL) 2.0V DD+ 10%V V IL-TTL Input Low Voltage (TTL)-0.3+0.8V V IH-5VT Input High Voltage (TTL 5V tolerant) 2.0V DD+ 1.8V V IL-5VT Input Low Voltage (TTL 5V tolerant)-0.3+0.8V
±10μA
I LI Input Leakage Current (0.1 V ) V IN) V DD)
(all pins except those with internal pull-up/pull-down resis-
tors)
I LO Output Leakage Current (0.1 V ) V OUT) V DD)±15μA
60μA
I IH Input Leakage Current V IH= V DD- 0.1 V
(pins with internal pull-down resistors)
-60μA
I IL Input Leakage Current V IL= 0.1 V
(pins with internal pull-up resistors)
C IN Input Capacitance8pF
C OUT Output Capacitance8pF
C I/O I/O Capacitance10pF Notes: