Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops

Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops

Ioannis L.Syllaios,Member,IEEE,and Poras T.Balsara,Senior Member,IEEE

Abstract—All-digital phase-locked loops(ADPLL)are inher-ently multirate systems with time-varying behavior.In support of this statement linear time-variant(LTV)models of ADPLL are presented that capture spectral aliasing effects that are not captured by linear time-invariant(LTI)models.It is analytically shown that the latter are subset of the former.The high-speed modulator that improves the frequency resolution of the digitally-controlled oscillator(DCO)is included,too.It realizes fractional resampling and interpolation of the tuning data of the DCO.The noise transfer from all three operating clock domains of the ADPLL(reference,,and DCO)to its output phase is accurately predicted and design metrics are derived with regard to its folded close-in and far-out phase noise performance.The analytical results are validated via simulations using measured event-driven modeling techniques for a CMOS RF ADPLL. Index Terms—All-digital phase-locked loops(ADPLL),fre-quency synthesizers,jitter transfer,linear time-variant(LTV) analysis,multirate modeling,noise folding,phase noise transfer, resampling,sigma-delta modulation,time-domain simulation.

I.I NTRODUCTION

A DV ANCED low-voltage nanometer-scale CMOS pro-

cesses allow for a large degree of scalability and integration of digital circuitry but greatly increase the de-sign cycle of pure analog or mixed-signal components due to poor process characterization and parameter spread. High-performance frequency synthesis circuits are tradition-ally implemented using a charge-pump phase-locked loop (PLL)with a voltage-controlled oscillator(VCO).In the effort to migrate such analog-centric circuits in the digital-centric regime,recent all-digital PLL(ADPLL)developments ex-plore the fast switching characteristics of MOS transistors of advanced CMOS processes to replace the charge-pump with a time-to-digital converter(TDC)and the VCO with a digi-tally-controlled oscillator(DCO)[1]–[5].The block diagram of a modern ADPLL frequency synthesizer is shown in Fig.1. The quantized bit-to-frequency and time-to-bit conversions in the DCO and the TDC,respectively,result in the generation of synthesized clock signals with reduced spectral purity compared to the synthesized clock signals of high-performance analog-centric counterpart topologies[6],[7].However,?ne bit-to-fre-quency resolution is typically achieved by means of high-speed

Manuscript received June14,2011;revised October03,2011;accepted De-cember31,2011.Date of publication March19,2012;date of current version October24,2012.This paper was recommended by Associate Editor S.-H.Cho.

I.L.Syllaios was with the Department of Electrical Engineering,University of Texas at Dallas,Richardson,TX75083USA.He now is with Broadcom Corp.,Irvine,CA92617USA(e-mail:syllaios@https://www.sodocs.net/doc/922492223.html,).

P.T.Balsara is with the Department of Electrical Engineering,University of Texas at Dallas,Richardson,TX75083USA(e-mail:poras@https://www.sodocs.net/doc/922492223.html,). Color versions of one or more of the?gures in this

paper are available online at https://www.sodocs.net/doc/922492223.html,.

Digital Object Identi?er10.1109/TCSI.2012.2189061Fig.1.Block diagram of a modern ADPLL frequency synthesizer.

dithering of the DCO tuning varactors by exercising?ex-ible-rate clock signals that are derived from the DCO itself using frequency division[8].Similarly,?ne time-to-bit resolution is achieved by employing TDC that realize noise-shaping[2],[9] or time ampli?cation[3].

The operation of a PLL involves in principle two clock sig-nals;the clock of a controlled oscillator(here,the DCO clock )and a very stable reference clock that is normally provided by a crystal oscillator(XO).Under frequency/phase lock conditions the frequency of is a multiple of the fre-quency of according to1Hz,where is the frequency control word(FCW)as shown in Fig.1.For RF wireless applications lies in the range of a few tens of MHz and in the GHz range.

The phase-domain is the natural domain of operation of PLL [10].They operate on the phase/frequency difference between

and the clock of the controlled oscillator under a phase detection mechanism that runs at the-rate.Furthermore,in case of ADPLL,the continuous-time phase information of those clocks is digitally regenerated and represented by discrete-time signals as highlighted in Fig.1.Speci?cally,the reference clock phase data are generated by-rate accumulation of FCW cycles and the composite phase data of are generated with the combination of-rate accumulation of integer cycles and the TDC,which is employed for fractional phase estimation. The resulting phase data of the DCO clock are synchro-nously resampled at the-rate in order to be compared with and produce the phase error data.The latter are?ltered through the digital loop?lter and subsequently control the fre-quency of the DCO by means of the tuning word(TW).Fi-nally,it is often necessary to interpolate the TW data in order to?ne-tune the DCO.A modulator is normally employed 1indicates a clock signal and its frequency.

1549-8328/$31.00?2012IEEE

for this purpose to resample the TW at a high frequency

Hz and subsequently dither the tuning varactors of the DCO in order to improve its effective frequency resolution.

The foregoing discussion highlights that ADPLL are inher-ently multirate systems and as such their multiple signal inter-polation and downsampling operations result in spectral aliasing effects that may degrade their performance[11].Such effects become apparent at the ADPLL output as increased close-in phase noise power spectral density(PSD)due to the folding of high-rate noise such as the phase noise of the DCO and the far-out shaped quantization noise of the modulator or as ex-cessive spurious tones that originate from the harmonic aliasing of limit cycle oscillations in the ADPLL due to its internal?-nite-precision arithmetic operations and the periodic variations of the DCO phase due to coupling and noise in the power supply and substrate[12].

Traditional models of ADPLL are based on linear time-in-variant(LTI)either continuous-time(-domain)or single-rate (i.e.,-rate)discrete-time(-domain)models that are de-rived from sampled-data models using the impulse-invariant transformation method[13]–[17].Such models have served as design basis for both ADPLL and analog charge-pump PLL (CPLL)for the past several years offering adequate predic-tion of their close-in?ltering performance.However,when compared against to sampled-data models they fail to capture the subsampling of the PLL output phase that occurs in the feedback path of the PLL and consequently the folding effects related to it.For these reasons,the loop bandwidth of PLL is designed to only be a fraction of the reference clock frequency (Hz)so that their sampled-data operation is not emphasized in the form of dynamic peaking or instability. Furthermore,the frequency domain analysis of PLL when conducted with-rate-domain models is constrained to the reference clock domain(i.e.,in Hz) and hence does not capture far-out PSD degradations due to the injection of higher-rate noise in the system.It is worth mentioning a recent work[18]that addressed the standalone limitation of a-rate-domain model to predict the folding of VCO phase noise in CPLL by combining it with the contin-uous-time forward path of its originating sampled-data model. The estimation of the folded phase noise power necessitated the modi?cation of the VCO noise source(i.e.,subsampling at the-rate and concurrent injection with the continuous-time noise source)followed by postprocessing of the generated output phase spectral images.

A linear discrete-time multirate model of ADPLL is proposed in this paper to address the limitations of traditional single-rate models to capture spectral aliasing effects that are associated with the actual digital multirate operation of ADPLL.It is sup-ported by solid linear time-variant(LTV)mathematical anal-ysis that accurately predicts the noise transfer from all consid-ered operating clock domains(,and)to the ADPLL output phase.It is analytically shown that the separately modeled noise transfers from the various clock domains of the ADPLL to its output phase converge in a single LTV model with superset structure that reveals how LTI analysis is linked to the LTV analysis of multirate systems in general.In particular,it is shown that their LTV output is effectively their LTI output ?ltered by a periodically time-varying recursive?lter.The so-lution of such a?lter is key for their complete LTV analysis across all their operating clock domains and is provided here in the context of the proposed multirate ADPLL model.This paper extends our work in[11]to account for the fact that the mod-ulator in addition to injecting high-rate quantization noise in the ADPLL it also realizes fractional resampling and interpolation of the tuning data of the DCO.

The folding of the quantization noise of the modulator was studied in[19]in the context of an open loop-rate accu-mulate-and-dump process that overestimated the folded quanti-zation noise power because it bypassed its intermediate interpo-lation at the-rate and integration in the DCO prior to sub-sampling in the TDC.The linearized analysis of jitter transfer in divider-based digital bang-bang PLL was studied in[20]using a discrete-time multirate model,which although accounted for the two clock-domain operation of the studied PLL,it did not accurately capture the jitter folding effects because its feedback divider model included a moving average?lter that attenuated the high frequency content of the PLL output jitter prior to its subsampling.Contrary to[20],a linear discrete-time multirate (two clock-domain)model was proposed in[21]and[22]for the jitter analysis of CPLL where although the effect of the feed-back divider on jitter was accurately modeled as a simple dec-imation operator that outputs one out of every transitions of the CPLL output clock,the followed methodology masked the linkage between LTI analysis and LTV analysis of multirate sys-tems.From the above discussion,it can be concluded that both divider-less ADPLL with actual digital multirate operation and divider-based PLL topologies with effective multirate in-loop jitter propagation share a common ground for their analysis to be conducted using multirate signal processing techniques. Section II develops the proposed linear discrete-time multi-rate model for the ADPLL in Fig.1in the context of integer-operation.The presented methodology is easily extended to ac-count for the fractional-operation,too.Section III performs LTV analysis and leads to the superset LTV model that clearly re?ects the periodically time-varying behavior of ADPLL. Section IV complements Section III with the solution of the periodically time-varying recursive?lter that completes the LTV analysis of multirate systems.Section V derives design metrics that accurately predict the degradation of the close-in phase noise performance of ADPLL due to the aliasing of the DCO phase noise and the far-out shaped quantization noise of the modulator when they are subsampled in the TDC and Section VI validates the analysis via measured time-domain simulation techniques for a CMOS RF ADPLL[23].

II.L INEAR D ISCRETE-T IME M ULTIRATE M ODELING OF

A LL-D IGITAL PLL

The sampled-data(mixed-type)discrete/continuous-time ADPLL model shown in Fig.2serves as the means for transi-tioning to a discrete-time multirate model that closely captures the multirate phase-domain operation of the ADPLL in Fig.1. It was recently proposed in[24]in its simplest form(without the modulator,per the needs of[24])and is enhanced here to account for the fractional interpolation of the-rate TW through the modulator prior to its application to the DCO. The clock signal is derived from the DCO by frequency division with an integer factor,i.e.,.The

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Fig.2.Sampled-data(mixed-type)discrete/continuous-time model of the ADPLL frequency synthesizer in Fig.

1.

Fig.3.Multirate model of the DCO.ZOH interpolation of the dithered tuning data by factor(:integer)and phase accumulation. primary advantages of the discrete-time multirate modeling approach over the continuous-time sample-data one is that on one hand is closer to the actual digital multirate operation of ADPLL and on the other hand results in compact analytical formulations because it is constrained to their fastest clock do-main,here in Hz,where for all practical purposes the energy of the subsampled ADPLL output phase is suf?ciently allocated to only a?nite number of spectral images as dictated by.

The transition from the clock domain to the clock domain is modeled with a zero-order-hold(ZOH)operator that mimics the?ip-?op register that applies the interpolated tuning word to the DCO.It is noted that the ZOH operator could be replaced by a more elaborate operator that incorporates the settling behavior of the DCO,too.Although,a simple ZOH in-terface is considered here the?nal analytical results maintain a generic form that can account for second order effects by a simple transfer function replacement.

The continuous-time transfer function of the DCO phase inte-grator with the ZOH interface that reconstructs the data is converted to a discrete-time-rate transfer function using the impulse-invariant transformation method.That is by mathe-matically sampling the continuous-time phase impulse response of the DCO at the-rate in order to capture its development at the rising(or falling)edges of and taking the-trans-form as shown in(1).The resulting discrete-time model of the DCO is shown in Fig.3.It is composed of a-rate integrator succeeded by a discrete-time ZOH reconstruction?lter that in-terpolates the upsampled data prior to phase accumula-tion in the integrator.

(1) In(1),is the-domain transfer function of the ZOH ?lter with and is the -rate-domain transfer function of the discrete-time ZOH interpolation?lter with. The modulator in

addition to injecting-rate quan-tization noise in the ADPLL it also realizes fractional resam-pling and interpolation of the-rate TW data.The resam-pling process is modeled as ZOH interpolation by noninteger Fig.4.Multirate model of the modulator.Fractional resampling of the -rate TW data at the-rate and dithering.

(in general)factor

where and

(are integers and gcd is the greatest common divisor). That is,the transition from the domain to the do-main necessitates an effective sampling rate increase by a factor followed by a sampling rate decrease by a factor,with and,respectively.The complete model of the modulator is shown in Fig.4.It is noted that although the integer-operation is considered in this paper as a driver for introducing the principles for the LTV analysis of ADPLL, the above methodology for modeling the resampling of the TW data in the modulator as fractional-interpolation can also be applied to the modeling of the fractional-operation of PLL.The fractional-operation will be addressed in a future article.

Contrary to PLL topologies that include a frequency divider in their feedback path,in ADPLL with the topology of Fig.1, the DCO phase is directly sampled in the TDC without division. Therefore,a decimation operator naturally replaces the sampler in the feedback path of the sampled-data model in Fig.2in order to interface the discrete-time-rate DCO model of Fig.3 with the-rate section of the ADPLL.

The complete linear discrete-time multirate ADPLL model is shown in Fig.5and it serves as the basis for the LTV analysis of ADPLL that is presented in the following section. It accounts for the coexistence of the three clock domains that are typically involved with its operation(,and )as well as the primary noise sources per clock domain. These are the phase noise of the XO and the induced phase noise due to the?nite resolution of the TDC,both combined in,the quantization noise of the modulator and the phase noise of the DCO(are integer indexes). The noise of XO and the DCO are respectively mod-eled as-rate and-rate discrete-time random sequences that re?ect the absolute jitter of the corresponding clock signal [25].The ADPLL model parameters in Fig.5are listed below.

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Fig.5.Discrete-time multirate model of the ADPLL frequency synthesizer in Fig.1.

?:The discrete-time angular frequency that de ?nes the

clock domain.rad.

?:The discrete-time angular frequency that de ?nes the clock domain.rad.

?:The discrete-time angular frequency that de ?nes the clock domain.rad.

?:The discrete-time angular frequency that de ?nes the virtual clock domain.rad.

?:The spectrum of the ADPLL output phase.?:The spectrum of the DCO phase noise.

?:The spectrum of the quantization noise of the

modulator.

?:The spectrum of the -rate resampled TW.?:The spectrum of the reference source.?:The spectrum of the phase error signal ..?:The spectrum of the -rate downsampled

output phase of the ADPLL.

?:The spectrum of the -rate interpolated TW.?:The -rate transfer function of the DCO phase integrator..is the DCO gain in Hz/LSB and sec.

?:The -rate transfer function of the ZOH

?lter that interpolates the -rate modulator output.

.

?:The -rate signal transfer function of the

modulator.

?:The -rate quantization noise transfer func-tion of the modulator.

?:The -rate transfer function of the ZOH ?lter

that interfaces the domain with the domain.

.

?:The -rate loop ?lter transfer function.

III.L INEAR T IME -V ARIANT (LTV)A NALYSIS OF A LL -D IGITAL

PLL A frequency-domain approach is followed for the LTV anal-ysis of the ADPLL using the discrete-time multirate model of Fig.5.Here,the transfer of the DCO phase noise to the ADPLL output phase is detailed and the derivation of the transfer charac-teristics for the remaining noise sources follow the same guide-lines.The superposition principle applies for the total output spectrum on the linearity basis of the model.

The output phase of the ADPLL due to the phase noise of the

DCO is found as follows:

(2)

According to the discussion in Section II,results after frac-tional resampling and interpolation of the -rate TW.The transition from the domain to the domain is math-ematically described by -rate ZOH interpolation fol-lowed by sampling rate decrease by factor .The integer fac-tors and re ?ect the smallest integers whose ratio equals to and depending on the values of (and hence those of )a virtual clock domain is de ?ned with

Hz that serves as the means

for the fractional-interpolation of the -rate TW at the

-rate.Therefore,the resampled -rate is effectively

the downsampled

and their spectrums are described by (3)and (4),respectively [26],[27].

(3)(4)

The spectrum of the subsampled output phase of the ADPLL

at the output of the TDC completes (4)and is given as

(5)

After placing (3)–(5)in (2)

is found as

(6)

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Fig.6.Magnitude responses of and for a type-II second-order ADPLL with MHz, GHz MHz

kHz/LSB and error-free DCO gain normalization.

where is a high-pass transfer function seen by the DCO phase noise,is a low-pass transfer function,inherent in the ADPLL structure,seen by the images of the output phase spectrum at integer multiples of Hz due to subsam-pling of the DCO phase in the TDC,and is a band-pass transfer function,also inherent in the ADPLL structure,seen by the images of the subsampled output phase at integer mul-tiples of Hz that result after resampling the-rate TW at the-rate.They are formulated as

(7)

(8)

(9) where

A realization of the magnitude responses of

and is shown in Fig.6.

Following the same procedure for the noise sources that orig-inate from the and clock domains,it is found that the spectrum of the output phase of the ADPLL has a similar ex-pression as(6)with the exception that is replaced by the interpolative transfer functions seen by the reference source and the induced quantization noise of the modulator.They are described by(10)and(11),respectively.

(10)

(11) The superposition of the individual output spectra contribu-tions from the three clock domains results in the total spectrum of the ADPLL output phase.It is analytically expressed by the superset equation(12)and on its basis the discrete-time multirate ADPLL model in Fig.5can be equivalently redrawn as shown in Fig.7.The?rst term of(12),[expanded in(13)],a natural outcome of the presented re?ects the output phase spectrum that is predicted after traditional LTI analysis of the discrete-time multirate ADPLL model in Fig.5.That is,by neglecting the spectral images of a down-sampled-by-discrete-time signal or,equivalently,by assuming that.

(12)

(13) The periodically time-varying coef?cients of the LTV model in Fig.7clearly re?ect the time-varying behavior of the ADPLL and its superset structure encompasses the traditional LTI models,too.The scope of LTI models is limited to its upper left section and its right section indicates that LTV models are equivalent to LTI models with a periodically time-varying recursive?ltering operation applied to their output.Such time-varying?ltering operation is effectively the result of sub-sampling the DCO phase with the reference clock in the TDC and subsequently resampling it via the TW in the modu-lator.The?rst operation results in the frequency translation of the ADPLL output phase spectrum at integer multiples of the reference clock frequency and the second one in its additional translations at integer multiples of the modulator clock frequency.These frequency translations are attributed to the two sets of periodically time-varying coef?cients of the LTV model and their effect becomes apparent at the ADPLL output as increased close-in phase noise power due to the folding of high-rate noise that is injected in the system such as the phase noise of the DCO and the far-out shaped quantization noise of the modulator,or as excessive spurious tones that originate from the harmonic aliasing of periodic signals in the ADPLL.The signal spectral images that are generated due to the multirate operation of the ADPLL are inherently?ltered by and.

A close of the LTV model in Fig.7reveals that the subsampling of the ADPLL output phase in the TDC(see the upper right section of the LTV model)directly impacts the close-in phase noise performance of the ADPLL because of the effective all-pass response of at small frequency offsets (see Fig.6).On the other hand,folded phase noise power due to the resampling of the phase error signal via the TW in the modulator(see the lower section of the LTV model)has minimal effect on the close-in phase noise performance of the ADPLL because of the high-pass response of at small frequency offsets(see Fig.6).Furthermore,under frequency/phase lock conditions of a practical ADPLL system it is expected that the phase error noise power is low and in conjunction with a

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Fig.7.Linear time-variant model of the ADPLL frequency synthesizer in Fig.1,as per(12).The lower section in the dashed line highlights the effect of the modulator on the phase error performance of the ADPLL.The upper left section highlights that LTI analysis is subset of LTV analysis.

dithering clock with frequency that satis?es the Nyquist crite-rion Hz,the effect of resampling the TW on the phase noise performance of the ADPLL is negligible.It can thus be concluded that for noise analysis purposes the third term of (12)can safely be neglected to only account for the primary second-order effects that result after subsampling the ADPLL output phase in the TDC,i.e.,

(14) It is worth noting that when the ratio is in-teger(i.e.,),(12)is naturally reduced to(14)and the lower section of the LTV model vanishes.The solution of(14) is key for the complete LTV analysis of the ADPLL across all its operating clock domains and is provided next.

IV.S OLUTION FOR(14)

Equation(14)describes the fundamental LTV system shown in Fig.8that bridges the LTI with the LTV analysis of mul-tirate systems.Its solution is provided here in the context of ADPLL following a frequency-domain approach.Speci?cally, the images of at integer multiples of the reference clock frequency,re?ected in for

,are?rst extracted by rotating. This is easier facilitated after transforming(14)to a suitable form that allows us to take advantage of the periodicity of the discrete-time Fourier transform.To this end,the sum on the right-hand side of(14)is?rst completed as

(15) and with the assistance of(5)the spectrum of the ADPLL output phase is equivalently expressed as

(16) where

(17)

(18) Equation(16)is rotated by replacing with

and the resulting images for are added to yield

(19)

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Fig.8.Fundamental LTV system as per(14)that bridges the LTI with the LTV analysis of ADPLL.It describes how the subsampling of the DCO phase in the TDC affects the output phase of the ADPLL.

where is periodic with period rad.is now replaced by

to?nd the extracted spectrum of images of

(20) The solution of(14)is analytically given by(21),which results after replacing the second term of(14)with(20)and solving with respect to.

(21) where

(22)

(23)

A realization of the magnitude responses of and

is shown in Fig.9.It can be seen that for all practical purposes and,which leads to the following simpli?cation of(21)

[11]:

(24)Fig.9.Magnitude responses of(22)and(23)for the same con?guration of the ADPLL as in Fig.6.The magnitude response of is also shown for comparison purposes with(23).

Fig.10.Single-sided(half-power)PSD of the DCO phase noise pro?le.

On the basis of(24)the PSD of the ADPLL output phase for uncorrelated noise sources is obtained as

(25) where

(26) V.ADPLL O UTPUT C LOSE-I N P LATEAU OF F OLDED DCO P HASE N OISE AND Q UANTIZATION N OISE

A.Close-In Plateau of Folded DCO Phase Noise

The phase noise spectrum of the DCO is described by the phase noise pro?le shown in Fig.10.It is composed of the three

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regions that are typically observed in measurements,namely the thermal(0dB/dec),the wander(20dB/dec)and the?icker (30dB/dec).They re?ect the non-accumulative thermal phase noise and the accumulative thermal and?icker phase noise of the DCO,respectively.

Equation(27)describes the phase noise pro?le of the DCO in rad/Hz in conjunction with the speci?cations shown in Fig.10.It is used for the calculation of the ADPLL output close-in plateau that results after the subsampling of the DCO phase noise in the TDC.

(27) In(27),rad/sec,is the thermal phase noise ?oor and the(power density,frequency offset)pairs

and de?ne the20dB/dec and30dB/dec regions of the phase noise pro?le of the DCO shown in Fig.10,respec-tively.

is obtained using(29),which results after evaluating the term of(25)at rad(i.e.,at the center frequency of the DCO clock)for

(28) Equation(28)in(25)reveals that when the phase noise of the DCO is subsampled in the TDC is frequency translated un?l-tered by and because of the effective all-pass response of at small frequency offsets directly impacts the phase noise performance of the ADPLL.

(29) In(29)a large value for was assumed for the ap-proximation of the summations and

with and1.2,respectively.The second and third terms of(29)agree with the?ndings in[18]in the context of the phase noise of a VCO in CPLL by determining and

at Hz,respectively.

The power density of the colored(wander and?icker)phase noise of the DCO of a well-designed ADPLL should be equal to or lower than the phase noise plateau that is contributed from the quantization noise of the TDC at the loop bandwidth frequency offset,which is normally constrained in the range of up to a few hundreds of kHz.For a today’s nanometer scale CMOS process technology the latter would correspond to dBc/Hz for a TDC with a

near ps resolution,a DCO clock in the1.5GHz range and a reference clock frequency of a few tens of MHz.was estimated Fig.11.ADPLL output

close-in plateau(normalized to)due to the folded thermal phase noise of the DCO,as the?rst term of(29).

Fig.12.ADPLL output close-in plateau(normalized to and) due to the wander and?icker phase noise of the DCO as per the second term and third term of(29),respectively..

using the formula

[28].Under the assumption that the ADPLL loop bandwidth

Hz and that at

Hz,in the absence of thermal phase noise, the second and third terms of(29)would induce a close-in plateau equal to

(30) It can therefore be concluded that the contribution of the colored phase noise of the DCO to the close-in folded phase noise power is negligible and that the latter is practically dominated by its thermal phase noise(see also Figs.11and12).The foregoing discussion leads to the rule of thumb(31)that the thermal phase noise?oor of the DCO should satisfy so that does not affect the close-in noise performance of the Equation(31)accounts for the thermal phase noise?oor of the reference clock,too.

(31)

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Fig.13.ADPLL output close-in plateau(normalized to)in-duced by a?rst order modulator,as per(33)[for].

B.Close-In Plateau of Folded Quantization Noise

The ADPLL output close-in plateau of the folded far-out quantization noise of the is obtained using(33)after evaluating the second term of(25)at

rad for

(32) The factor has been introduced for proper scaling.

(33) In(33)the DCO gain is de?ned in Hz/LSB and is the order of the high-pass transfer function

that shapes the quantization noise of a MASH modulator [29]–[31].Its quantization noise is considered white with PSD

for Hz.

has been evaluated for typically used division fac-tors and plotted normalized with respect to in Figs.13–15for up to third-order modulators,respectively. The dashed lines correspond to the values of that sat-isfy the boundary condition of the relation(i.e., ),which re?ects the Nyquist criterion

Hz.

Equation(32)can also be used for the prediction of the far-out peaking of the ADPLL output phase noise spectrum near

Hz that results from the high-pass noise shaping functionality of the modulator.The power density in rad/Hz of this local maximum is obtained by(34)at,the frequency of the?rst maximum of

(32).

(34)Fig.14.Similarly as in Fig.13for a third order modulator,as per(33)[for ].

Fig.15.Similarly as in Fig.13for a second order modulator,as per(33) [for].

A close inspection of(34)in conjunction with(32)reveals that the far-out high-pass noise shaping functionality of a?rst-order modulator is masked by the phase integrator of the DCO and its ZOH interface.In particular,for it is converted to an effective all-pass?lter and for to a moving average?lter with variable dc gain.However,higher-order modulators behave as expected for all values of.has been evaluated for the same division factors and modulator orders as in Figs.13–15and plotted normalized with respect to in Fig.16.For the case where and frequency re?ects the3-d

B bandwidth of the moving average?lter with transfer function.

Figs.13–16may be utilized as design guides for the optimal selection of the modulator order and its frequency of op-eration through the value of,given far-out and close-in PSD speci?cations.Although a?rst-order modulator would in theory always produce the lowest far-out and close-in power density levels for a given set of values,its typical realization as a digital accumulator renders it impractical for its intended purpose,which is the improvement of the effec-tive frequency resolution of the DCO.This is because a digital accumulator has very poor phase error randomization properties

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Fig.16.ADPLL output far-out peak PSD near Hz(normalized to)that results from the shaping func-

modulator,as per(34).

[32],[33]that mask its underlined high-pass noise shaping char-acteristic even under the self-dithered operation of the ADPLL. For these reasons higher order modulators are preferred that are based on a MASH(Multi-stAge noise-SHaping)structure of cascaded digital accumulators that often employ additional dithering mechanisms for spur-free operation[34],[35].

VI.V ALIDATION

The proposed linear discrete-time multirate ADPLL model in Fig.5and its LTV analysis are validated in this section via time-domain simulations.They are based on event-driven modeling techniques for ADPLL that have been validated with measurements of an actual CMOS RF ADPLL[23].A type-II second-order system has been selected with loop?lter transfer function,which results in a loop with damping factor and bandwidth MHz for a reference clock frequency MHz.Although a practical RF ADPLL would require a much smaller loop bandwidth so that spurious tones due to its?nite-precision arithmetic are adequately suppressed,here this requirement is relaxed and ?oating-point arithmetic is assumed so that the noise aliasing effects are clearly visible at small frequency offsets(kHz). The resolution of the TDC is chosen to be ps,which for a DCO clock with frequency GHz results in an output close-in plateau

(35) The PSD of the colored(wander and?icker)phase noise of the DCO at MHz offset is de-?ned to be dBc/Hz.However, without deviating from the scope of this paper,the?icker phase noise of the DCO is neglected in order to allow an additional 10dB/dec headroom on top of its40dB/dec high-pass atten-uated wander phase noise for the folded ADPLL output phase noise to be clearly visible.According to(29)both the wander and the?icker phase noise independently have minor effect to the ADPLL output close-in folded phase noise power[see(36)and(37),respectively].Equation(37)justi?es that the?icker phase noise of the DCO can safely be neglected.Finally,the phase noise of the reference clock(XO)is ignored since its pur-pose in this paper is served through the-rate quantization noise of the TDC being captured in.

(36)

(37) The presented LTV analysis is validated via two represen-tative simulations that explore(29)–(31),which pertain to the design speci?cation of the DCO phase noise and(33)–(34), which pertain to the optimal selection of the order and operating frequency of the modulator,given a far-out peak power density level requirement.The DCO gain is?to500 kHz/LSB and.

?Simulation-1:The power of the thermal phase noise of the DCO is set according to(38)so that after subsampling in the TDC induces a close-in https://www.sodocs.net/doc/922492223.html,ing

(29)and after neglecting its colored phase noise the above

requirement corresponds to

(38)

A third-order modulator is initially selected and its op-

eration frequency is set by means of

so that.This would result in a dB increase the output PSD level above

near Hz.This requirement is chosen here to vali-date the ability of the presented LTV analysis to accurately predict the ADPLL output spectrum beyond the reference clock domain frequencies(i.e.,for Hz).Ac-cording to Figs.16and14a division factor leads to MHz and the following peak(at45.634 MHz)and folded power densities,respectively:

(39)

(40)

Based on the above conditions the composite spectrum of the ADPLL output phase noise should be in line with the following far-out peak,aliased and total close-in plateaus:

(41)

(42)

(43)

(44)

The analytically derived PSD of the ADPLL output phase noise using(25)and(26)are shown in Fig.17superim-posed on the PSD of the phase noise data of the ADPLL

SYLLAIOS AND BALSARA:LINEAR TIME-V ARIANT MODELING AND ANALYSIS OF ALL-DIGITAL PHASE-LOCKED LOOPS2505

output clock timestamps,proving the conditions of Simu-lation-1hence the validity of the presented discrete-time multirate ADPLL model and LTV analysis.?Simulation-2:The power of the thermal phase noise of the DCO is set according to(45)so that after subsampling in the TDC induces a close-in plateau that is10dB lower than .This condition re?ects the rule of thumb(31).Using

(29)and after neglecting its colored phase noise the above

requirement corresponds to

(45)

Fig.16is used to optimize the order and operation fre-quency of the modulator so that is also re-duced by10dB compared to(39).A10dB improvement in can be achieved by either reducing to(a

2.33increase in)or by switching to a second-order

modulator and reducing to(a1.56increase in).The second approach is followed here,which ac-cording to Fig.16and15leads to the following peak(at

59.074MHz)and folded power densities:

(46)

(47)

Based on the above conditions the composite spectrum of the ADPLL output phase noise should be in line with the following far-out peak,aliased and total close-in plateaus:

(48)

(49)

(50)

(51)

The analytically derived PSD of the ADPLL output phase noise using(25)and(26)are shown in Fig.18superim-posed on the PSD of the phase noise data of the ADPLL output clock timestamps.They prove the conditions of Simulation-2and highlight that the optimization of the high-rate noise sources of the ADPLL,such as the DCO and the modulator,in accordance with the presented LTV analysis can drastically improve their related noise aliasing effects and give rise to an effective LTI behavior.

VII.C ONLCUSION

In this article,a linear discrete-time multirate model for all-digital PLL(ADPLL)has been proposed to address the limitations of traditional linear time-invariant(LTI)single-rate models to capture spectral aliasing effects that are associated with their actual digital multirate operation.The high-speed modulator that is normally employed for the improvement of the effective frequency

resolution of the digitally-controlled oscillator(DCO)has been included,too.In addition to injecting Fig.

17.Simulated and analytically predicted PSD of the ADPLL output clock phase noise,per Simulation-1.

Fig.18.Simulated and analytically predicted PSD of the ADPLL output clock phase noise,per Simulation-2.

high-rate quantization noise in the ADPLL it also realizes frac-tional resampling and interpolation of the tuning data of the DCO.The noise transfer from all considered operating clock domains of the ADPLL(reference,,and DCO)to its output phase has been predicted using linear time-variant(LTV) analysis and design metrics have been derived with reference to its folded close-in and far-out phase noise performance.It was shown that the separately modeled noise transfers from the various clock domains of the ADPLL to its output phase converge in a single LTV model with superset structure that reveals the linkage between LTI and LTV analysis of multirate systems in general.Speci?cally,it was shown that their LTV output is effectively their LTI output?ltered by a periodically time-varying recursive?lter.The solution of such?lter is key for their complete LTV analysis across all their operating clock domains and has been provided here in the context of the proposed multirate ADPLL model.The analytical results have been validated via simulations using measured event-driven time-domain modeling techniques for a CMOS RF ADPLL.

2506IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I:REGULAR PAPERS,VOL.59,NO.11,NOVEMBER2012

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Ioannis L.Syllaios received the B.S.E.E.(summa

cum laude),M.S.E.E.,and Ph.D.degrees from the

University of Texas at Dallas,Richardson,in2003,

2005,and2010,respectively.

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Poras T.Balsara(M’85–SM’95)received the

L.E.E.diploma in electronics from Victoria Jubilee

Technical Institute,Mumbai,India,in1980,the B.E.

(electrical)degree from the University of Bombay,

Mumbai,in1983,and the M.S.and Ph.D.degrees

from the Pennsylvania State University,University

Park,in1985and1989,respectively.

In1989,he joined the faculty of the Erik Jonsson

School of Engineering and Computer Science,

University of Texas at Dallas,Richardson,where is

currently a Professor of Electrical Engineering.He has published several journal and conference publications and has coauthored one book.His research interests include VLSI design,design of energy-ef?cient digital circuits and systems,circuits and systems for DSP and communications, computer arithmetic,and digitally assisted mixed-signal and power electronics circuits.His recent work includes the design of CMOS all-digital phase-locked loops(ADPLL)and other digitally intensive front-end circuits for wireless transceivers.

能源概论课后习题带答案

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合理想能源必要条件的是（） A、必须足够丰富，可以保证长期使用 B、必须足够便宜，可以保证多数人用得起 C、必须足够安全、清洁，可以保证不会严重影响环境 D、必须足够昂贵，可以保证节约使用 14、核电站的能量转化情况是（） A、核能→机械能→电能 B、核能→内能→机械能→电能 C、核能→化学能→电能 D、化学能→内能→电能 15、下列有关说法正确的是（） A、核能的释放主要是通过重核裂变和轻核聚变 B、核反应是不能控制的 C、放射性射线能用于治疗肿瘤，因此对人体无害 D、太阳能来源于太阳内部的重核裂变 16、水能资源最显著的优点不包括以下哪一点（） A、成本低 B、无污染 C、利用便利 D、可再生 17、关于开发利用风能的意义，理解正确的一组是（） ①节约大量化石燃料②风能是可再生能源③减少SO2排放，防止形成酸雨④风能是二次能源 A、①②③ B、①②④ C、①③④ D、②③④ 18、关于风能下列说法中，不正确的是（） A、不污染环境 B、不便于贮存 C、很稳定 D、利用起来很简单 19、我国著名的大型水电站不包括（） A、三峡水电站 B、小浪底水电站 C、葛洲坝水电站 D、大古力水电站 20、以下发电过程中利用了化学变化的是（） A、火力发电 B、水力发电 C、风力发电 D、地热发电 21、我国大型核电站有（） A、秦山核电站 B、大亚湾核电站 C、岭澳核电站 D、田湾核电站 22、关于核能，下列说法正确的是（） A、原子核很小，因此其中不可能存在大量的能量 B、人们现在能够利用可控核聚变的能量