PI TNY274开关电源芯片规格书
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Figure 1. Typical Standby Application. Product Highlights
Lowest System Cost with Enhanced Flexibility
? Simple ON/OFF control, no loop compensation needed
? Selectable current limit through BP/M capacitor value
- Higher current limit extends peak power or, in open frame applications, maximum continuous power - Lower current limit improves ef?ciency in enclosed adapters/chargers
- Allows optimum TinySwitch-III choice by swapping devices with no other circuit redesign
? Tight I 2f parameter tolerance reduces system cost - Maximizes MOSFET and magnetics power delivery - Minimizes max overload power, reducing cost of
transformer, primary clamp & secondary components
? ON-time extension – extends low line regulation range/hold-up time to reduce input bulk capacitance ? Self-biased: no bias winding or bias components ? Frequency jittering reduces EMI ?lter costs ? Pin-out simpli?es heatsinking to the PCB
? SOURCE pins are electrically quiet for low EMI
Enhanced Safety and Reliability Features ? Accurate hysteretic thermal shutdown protection with
automatic recovery eliminates need for manual reset
? Improved auto-restart delivers <3% of maximum power
in short circuit and open loop fault conditions
? Output overvoltage shutdown with optional Zener ? Line under-voltage detect threshold set using a single
optional resistor
? Very low component count enhances reliability and
enables single-sided printed circuit board layout ? High bandwidth provides fast turn on with no overshoot and excellent transient load response ? Extended creepage between DRAIN and all other pins improves ?eld reliability
EcoSmart ?
– Extremely Energy Ef?cient
? Easily meets all global energy ef?ciency regulations ? No-load <150 mW at 265 V AC without bias winding, <50 mW with bias winding
? ON/OFF control provides constant ef?ciency down to very light loads – ideal for mandatory CEC regulations and 1 W PC standby requirements
Applications
? Chargers/adapters for cell/cordless phones, PDAs, digital cameras, MP3/portable audio, shavers, etc.
February 2006
Table 1. Notes: 1. Minimum continuous power in a typical non-ventilated enclosed adapter measured at 50 °C ambient. Use of an external heatsink will increase power capability 2. Minimum peak
power capability in any design or minimum continuous power in an open frame design (see Key Application Considerations). 3. Packages:
P: DIP-8C, G: SMD-8C. See Part Ordering Information.? PC Standby and other auxiliary supplies
? DVD/PVR and other low power set top decoders
? Supplies for appliances, industrial systems, metering, etc.
Description
TinySwitch-III incorporates a 700 V power MOSFET, oscillator, high voltage switched current source, current limit (user selectable) and thermal shutdown circuitry. The IC family uses an ON/OFF control scheme and offers a design ?exible solution with a low system cost and extended power capability.
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Figure 2. Functional Block Diagram.
Figure 3. Pin Con?guration.
Pin Functional Description
DRAIN (D) Pin:
This pin is the power MOSFET drain connection. It provides internal operating current for both start-up and steady-state operation.
BYPASS/MULTI-FUNCTION (BP/M) Pin:This pin has multiple functions:
1. It is the connection point for an external bypass capacitor for the internally generated 5.85 V supply.
2. It is a mode selector for the current limit value, depending on the value of the capacitance added. Use of a 0.1 μF capacitor results in the standard current limit value. Use of a 1 μF capacitor results in the current limit being reduced to that of the next smaller device size. Use of a 10 μF capacitor results in the current limit being increased to that of the next larger device size for TNY275-280.
3. It provides a shutdown function. When the current into the bypass pin exceeds 5.5 mA, the device latches off until the BP/M voltage drops below
4.9 V , during a power down. This can be used to provide an output overvoltage function with a Zener connected from the BP/M pin to a bias winding supply.
ENABLE/UNDER-VOLTAGE (EN/UV) Pin:
This pin has dual functions: enable input and line under-voltage sense. During normal operation, switching of the power
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MOSFET is controlled by this pin. MOSFET switching is
terminated when a current greater than a threshold current is
drawn from this pin. Switching resumes when the current being
pulled from the pin drops to less than a threshold current. A
modulation of the threshold current reduces group pulsing. The
threshold current is between 60 μA and 115 μA.
The EN/UV pin also senses line under-voltage conditions through
an external resistor connected to the DC line voltage. If there is
no external resistor connected to this pin, TinySwitch-III detects
its absence and disables the line under-voltage function.
SOURCE (S) Pin:
This pin is internally connected to the output MOSFET source
for high voltage power return and control circuit common.
TinySwitch-III Functional
Description
TinySwitch-III combines a high voltage power MOSFET switch
with a power supply controller in one device. Unlike conventional
PWM (pulse width modulator) controllers, it uses a simple
ON/OFF control to regulate the output voltage.
The controller consists of an oscillator, enable circuit (sense and
logic), current limit state machine, 5.85 V regulator, BYPASS/
MULTI-FUNCTION pin under-voltage, overvoltage circuit, and
current limit selection circuitry, over- temperature protection,
current limit circuit, leading edge blanking, and a 700 V power
MOSFET. TinySwitch-III incorporates additional circuitry for
line under-voltage sense, auto-restart, adaptive switching cycle
on-time extension, and frequency jitter. Figure 2 shows the
functional block diagram with the most important features.
Oscillator
The typical oscillator frequency is internally set to an average
of 132 kHz. Two signals are generated from the oscillator: the
maximum duty cycle signal (DC
MAX
) and the clock signal that
indicates the beginning of each cycle.
The oscillator incorporates circuitry that introduces a small
amount of frequency jitter, typically 8 kHz peak-to-peak, to
minimize EMI emission. The modulation rate of the frequency
jitter is set to 1 kHz to optimize EMI reduction for both average
and quasi-peak emissions. The frequency jitter should be
measured with the oscilloscope triggered at the falling edge of
the DRAIN waveform. The waveform in Figure 4 illustrates
the frequency jitter.
Enable Input and Current Limit State Machine
The enable input circuit at the EN/UV pin consists of a low
impedance source follower output set at 1.2 V. The current
through the source follower is limited to 115 μA. When the
current out of this pin exceeds the threshold current, a low
logic level (disable) is generated at the output of the enable
circuit, until the current out of this pin is reduced to less than
the threshold current. This enable circuit output is sampled
at the beginning of each cycle on the rising edge of the clock
signal. If high, the power MOSFET is turned on for that cycle
(enabled). If low, the power MOSFET remains off (disabled).
Since the sampling is done only at the beginning of each cycle,
subsequent changes in the EN/UV pin voltage or current during
the remainder of the cycle are ignored.
The current limit state machine reduces the current limit by
discrete amounts at light loads when TinySwitch-III is likely to
switch in the audible frequency range. The lower current limit
raises the effective switching frequency above the audio range
and reduces the transformer ?ux density, including the associated
audible noise. The state machine monitors the sequence of
enable events to determine the load condition and adjusts the
current limit level accordingly in discrete amounts.
Under most operating conditions (except when close to no-load),
the low impedance of the source follower keeps the voltage on
the EN/UV pin from going much below 1.2 V in the disabled
state. This improves the response time of the optocoupler that
is usually connected to this pin.
5.85 V Regulator and
6.4 V Shunt Voltage Clamp
The 5.85 V regulator charges the bypass capacitor connected
to the BYPASS pin to 5.85 V by drawing a current from the
voltage on the DRAIN pin whenever the MOSFET is off. The
BYPASS/MULTI-FUNCTION pin is the internal supply voltage
node. When the MOSFET is on, the device operates from the
energy stored in the bypass capacitor. Extremely low power
consumption of the internal circuitry allows TinySwitch-III to
operate continuously from current it takes from the DRAIN
pin. A bypass capacitor value of 0.1 μF is suf?cient for both
high frequency decoupling and energy storage.
600
0510
136 kHz
128 kHz
V DRAIN
Time (μs)
P
I
-
2
7
4
1
500
400
300
200
100
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P I -4098-082305
25005000
Time (ms)
5010100200300
V DRAIN
V
DC-OUTPUT
In addition, there is a 6.4 V shunt regulator clamping the BYPASS/MULTI-FUNCTION pin at 6.4 V when current is provided to the BYPASS/MULTI-FUNCTION pin through an external resistor. This facilitates powering of TinySwitch-III externally through a bias winding to decrease the no-load consumption to well below 50 mW.
BYPASS/MULTI-FUNCTION Pin Under-Voltage
The BYPASS/MULTI-FUNCTION pin under-voltage circuitry disables the power MOSFET when the BYPASS/MULTI-FUNCTION pin voltage drops below 4.9 V in steady state operation. Once the BYPASS/MULTI-FUNCTION pin voltage drops below 4.9 V in steady state operation, it must rise back to 5.85 V to enable (turn-on) the power MOSFET.
Over Temperature Protection
The thermal shutdown circuitry senses the die temperature. The threshold is typically set at 142 °C with 75 °C hysteresis. When the die temperature rises above this threshold the power MOSFET is disabled and remains disabled until the die temperature falls by 75 °C, at which point it is re-enabled. A large hysteresis of 75 °C (typical) is provided to prevent overheating of the PC board due to a continuous fault condition.
Current Limit
The current limit circuit senses the current in the power MOSFET. When this current exceeds the internal threshold (I LIMIT ), the
power MOSFET is turned off for the remainder of that cycle. The current limit state machine reduces the current limit threshold
by discrete amounts under medium and light loads.
The leading edge blanking circuit inhibits the current limit comparator for a short time (t LEB ) after the power MOSFET is turned on. This leading edge blanking time has been set so that current spikes caused by capacitance and secondary-side recti?er reverse recovery time will not cause premature termination of the switching pulse.Auto-Restart
In the event of a fault condition such as output overload, output short circuit, or an open loop condition, TinySwitch-III enters into auto-restart operation. An internal counter clocked by the oscillator is reset every time the EN/UV pin is pulled low. If the EN/UV pin is not pulled low for 64 ms, the power MOSFET switching is normally disabled for 2.5 seconds (except in the case of line under-voltage condition, in which case it is disabled until the condition is removed). The auto-restart alternately enables and disables the switching of the power MOSFET until the fault condition is removed. Figure 5 illustrates auto-restart circuit operation in the presence of an output short circuit.In the event of a line under-voltage condition, the switching of the power MOSFET is disabled beyond its normal 2.5 seconds until the line under-voltage condition ends.
Adaptive Switching Cycle On-Time Extension
Adaptive switching cycle on-time extension keeps the cycle on until current limit is reached, instead of prematurely terminating after the DC MAX signal goes low. This feature reduces the minimum input voltage required to maintain regulation, extending hold-up time and minimizing the size of bulk capacitor required. The on-time extension is disabled during the startup of the power supply, until the power supply output reaches regulation.
Line Under-Voltage Sense Circuit The DC line voltage can be monitored by connecting an external resistor from the DC line to the EN/UV pin. During power-up or when the switching of the power MOSFET is disabled in auto-restart, the current into the EN/UV pin must exceed 25 μA to initiate switching of the power MOSFET. During power-up, this is accomplished by holding the BYPASS/MULTI-FUNCTION pin to 4.9 V while the line under-voltage condition exists. The BYPASS/MULTI-FUNCTION pin then rises from 4.9 V to 5.85 V w hen t he l ine u nder-voltage c ondition g oes a way. W hen t he
switching of the power MOSFET is disabled in auto-restart mode and a line under-voltage condition exists, the auto-restart counter
is stopped. This stretches the disable time beyond its normal 2.5 seconds until the line under-voltage condition ends.
The line under-voltage circuit also detects when there is no external resistor connected to the EN/UV pin (less than ~1 μA into the pin). In this case the line under-voltage function is disabled.
TinySwitch-III Operation
TinySwitch-III devices operate in the current limit mode. When enabled, the oscillator turns the power MOSFET on at the beginning of each cycle. The MOSFET is turned off when the current ramps up to the current limit or when the DC MAX limit is reached. Since the highest current limit level and frequency of a TinySwitch-III design are constant, the power delivered to the
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V DRAIN
V EN CLOCK DC
DRAIN
I MAX
PI-2749-082305
Figure 6. Operation at Near Maximum Loading.
V DRAIN
V EN
CLOCK DC
DRAIN I MAX
PI-2667-082305
Figure 8. Operation at Medium Loading.
Figure 7. Operation at Moderately Heavy Loading.load is proportional to the primary inductance of the transformer and peak primary current squared. Hence, designing the supply involves calculating the primary inductance of the transformer for the maximum output power required. If the TinySwitch-III is appropriately chosen for the power level, the current in the calculated inductance will ramp up to current limit before the DC MAX limit is reached.
Enable Function
TinySwitch-III senses the EN/UV pin to determine whether or
not to proceed with the next switching cycle. The sequence of cycles is used to determine the current limit. Once a cycle is started, it always completes the cycle (even when the EN/UV pin changes state half way through the cycle). This operation results in a power supply in which the output voltage ripple is determined by the output capacitor, amount of energy per switch cycle and the delay of the feedback.
The EN/UV pin signal is generated on the secondary by comparing the power supply output voltage with a reference voltage. The EN/UV pin signal is high when the power supply output voltage is less than the reference voltage.
In a typical implementation, the EN/UV pin is driven by an
optocoupler. The collector of the optocoupler transistor is connected to the EN/UV pin and the emitter is connected to the SOURCE pin. The optocoupler LED is connected in series with a Zener diode across the DC output voltage to be regulated. When the output voltage exceeds the target regulation voltage level (optocoupler LED voltage drop plus Zener voltage), the optocoupler LED will start to conduct, pulling the EN/UV pin low. The Zener diode can be replaced by a TL431 reference circuit for improved accuracy.
ON/OFF Operation with Current Limit State Machine The internal clock of the TinySwitch-III runs all the time. At
the beginning of each clock cycle, it samples the EN/UV pin to decide whether or not to implement a switch cycle, and based on the sequence of samples over multiple cycles, it determines the appropriate current limit. At high loads, the state machine sets the current limit to its highest value. At lighter loads, the state machine sets the current limit to reduced values.
PI-2377-082305
V DRAIN
V EN CLOCK DC
DRAIN
I MAX
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Figure 12. Normal Power-Down Timing (without UV).
Figure 13. Slow Power-Down Timing with Optional External
(4 M ?) UV Resistor Connected to EN/UV Pin.
Figure 10. Power-Up with Optional External UV Resistor (4 M ?) Connected to EN/UV Pin.
Figure 11. Power-Up Without Optional External UV Resistor Connected to EN/UV Pin.
PI-2661-082305
V DRAIN
V EN
CLOCK DC
DRAIN
I MAX
Figure 9. Operation at Very Light Load.
At near maximum load, TinySwitch-III will conduct during nearly all of its clock cycles (Figure 6). At slightly lower load,
it will “skip” additional cycles in order to maintain voltage
regulation at the power supply output (Figure 7). At medium loads, cycles will be skipped and the current limit will be reduced (Figure 8). At very light loads, the current limit will be reduced even further (Figure 9). Only a small percentage of cycles will
occur to satisfy the power consumption of the power supply.
The response time of the ON/OFF control scheme is very fast
compared to PWM control. This provides tight regulation and excellent transient response.
P I -230 2.55
Time (s)
1002004003000100200V
DC-INPUT
V
DRAIN 0
1
2Time (ms)020040050100100200P I -2383-030801
V
DC-INPUT
V
BYPASS V DRAIN 0
1
2
Time (ms)
020040050
10
0100200
.5
1
Time (s)
010********
100
200400
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Power Up/Down
The TinySwitch-III requires only a 0.1 μF capacitor on the BYPASS/MULTI-FUNCTION pin to operate with standard current limit. Because of its small size, the time to charge this capacitor is kept to an absolute minimum, typically 0.6 ms. The time to charge will vary in proportion to the BYPASS/MULTI-FUNCTION pin capacitor value when selecting different current limits. Due to the high bandwidth of the ON/OFF feedback, there is no overshoot at the power supply output. When an external resistor (4 M ?) is connected from the positive DC input to the EN/UV pin, the power MOSFET switching will be delayed during power-up until the DC line voltage exceeds the threshold (100 V). Figures 10 and 11 show the power-up timing waveform in applications with and without an external resistor (4 M ?) connected to the EN/UV pin.
Under startup and overload conditions, when the conduction time is less than 400 ns, the device reduces the switching frequency to maintain control of the peak drain current.
During power-down, when an external resistor is used, the power MOSFET will switch for 64 ms after the output loses regulation. The power MOSFET will then remain off without any glitches since the under-voltage function prohibits restart when the line voltage is low.
Figure 12 illustrates a typical power-down timing waveform. Figure 13 illustrates a very slow power-down timing waveform as in standby applications. The external resistor (4 M ?) is connected to the EN/UV pin in this case to prevent unwanted restarts.No bias winding is needed to provide power to the chip because it draws the power directly from the DRAIN pin (see Functional Description above). This has two main bene?ts. First, for a nominal application, this eliminates the cost of a bias winding and associated components. Secondly, for battery charger applications, the current-voltage characteristic often allows the output voltage to fall close to zero volts while still delivering power. TinySwitch-III accomplishes this without a forward bias winding and its many associated components. For applications that require very low no-load power consumption (50 mW), a resistor from a bias winding to the BYPASS/MULTI-FUNCTION pin can provide the power to the chip. The minimum recommended current supplied is 1 mA. The BYPASS/MULTI-FUNCTION pin in this case will be clamped at 6.4 V . This method will eliminate the power draw from the DRAIN pin, thereby reducing the no-load power consumption and improving full-load ef?ciency.
Current Limit Operation
Each switching cycle is terminated when the DRAIN current reaches the current limit of the device. Current limit operation provides good line ripple rejection and relatively constant power delivery independent of input voltage.
BYPASS/MULTI-FUNCTION Pin Capacitor
The BYPASS/MULTI-FUNCTION pin can use a ceramic capacitor as small as 0.1 μF for decoupling the internal power supply of the device. A larger capacitor size can be used to adjust the current limit. For TNY275-280, a 1 μF BP/M pin capacitor will select a lower current limit equal to the standard current limit of the next smaller device and a 10 μF BP/M pin capacitor will select a higher current limit equal to the standard current limit of the next larger device. The higher current limit level of
the TNY280 is set to 850 mA typical. The TNY274 MOSFET
does not have the capability for increased current limit so this feature is not available in this device.
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Applications Example
The circuit shown in Figure 14 is a low cost, high ef?ciency,
?yback power supply designed for 12 V, 1 A output from
universal input using the TNY278.
The supply features under-voltage lockout, primary sensed
output overvoltage latching shutdown protection, high
efficiency (>80%), and very low no-load consumption
(<50 mW at 265 V AC). Output regulation is accomplished using
a simple zener reference and optocoupler feedback.
The recti?ed and ?ltered input voltage is applied to the primary
winding of T1. The other side of the transformer primary is
driven by the integrated MOSFET in U1. Diode D5, C2, R1,
R2, and VR1 comprise the clamp circuit, limiting the leakage
inductance turn-off voltage spike on the DRAIN pin to a safe
value. The use of a combination a Zener clamp and parallel
RC optimizes both EMI and energy ef?ciency. Resistor R2
allows the use of a slow recovery, low cost, recti?er diode by
limiting the reverse current through D5. The selection of a
slow diode also improves ef?ciency and conducted EMI but
should be a glass passivated type, with a speci?ed recovery
time of ≤2 μs.
The output voltage is regulated by the Zener diode VR3. When
the output voltage exceeds the sum of the Zener and optocoupler
LED forward drop, current will ?ow in the optocoupler LED.
This will cause the transistor of the optocoupler to sink current.
When this current exceeds the ENABLE pin threshold current
the next switching cycle is inhibited. When the output voltage
falls below the feedback threshold, a conduction cycle is allowed
to occur and, by adjusting the number of enabled cycles, output
regulation is maintained. As the load reduces, the number of
enabled cycles decreases, lowering the effective switching
frequency and scaling switching losses with load. This provides
almost constant ef?ciency down to very light loads, ideal for
meeting energy ef?ciency requirements.
As the TinySwitch-III devices are completely self-powered,
there is no requirement for an auxiliary or bias winding on the
transformer. However by adding a bias winding, the output
overvoltage protection feature can be con?gured, protecting
the load against open feedback loop faults.
When an overvoltage condition occurs, such that bias voltage
exceeds the sum of VR2 and the BYPASS/MULTIFUNCTION
(BP/M) pin voltage (28 V+5.85 V), current begins to ?ow into the
BP/M pin. When this current exceeds 5 mA the internal latching
shutdown circuit in TinySwitch-III is activated. This condition
is reset when the BP/M pin voltage drops below 2.6 V after
removal of the AC input. In the example shown, on opening
the loop, the OVP trips at an output of 17 V.
Figure 14. TNY278P, 12 V, 1 A Universal Input Power Supply.
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For lower no-load input power consumption, the bias winding may also be used to supply the TinySwitch-III device. Resistor R8 feeds current into the BP/M pin, inhibiting the internal high voltage current source that normally maintains the BP/M pin capacitor voltage (C7) during the internal MOSFET off time. This reduces the no-load consumption of this design from 140 mW to 40 mW at 265 V AC.
Under-voltage lockout is con?gured by R5 connected between the DC bus and EN/UV pin of U1. When present, switching is inhibited until the current in the EN/UV pin exceeds 25 μA. This allows the startup voltage to be programmed within the normal operating input voltage range, preventing glitching of the output under abnormal low voltage conditions and also on removal of the AC input.
In addition to the simple input pi ?lter (C1, L1, C2) for
differential mode EMI, this design makes use of E-Shield ?
shielding techniques in the transformer to reduce common
mode EMI displacement currents, and R2 and C4 as a damping
network to reduce high frequency transformer ringing. These
techniques, combined with the frequency jitter of TNY278,
give excellent conducted and radiated EMI performance with
this design achieving >12 dB μV of margin to EN55022 Class
B conducted EMI limits.
For design ?exibility the value of C7 can be selected to pick one
of the 3 current limits options in U1. This allows the designer to select the current limit appropriate for the application.
? Standard current limit (I LIMIT ) is selected with a 0.1 μF BP/M
pin capacitor and is the normal choice for typical enclosed adapter applications.
? When a 1 μF BP/M pin capacitor is used, the current limit is reduced (I LIMITred or I LIMIT -1) offering reduced RMS device currents and therefore improved ef?ciency, but at the expense of maximum power capability. This is ideal for thermally challenging designs where dissipation must be minimized.
? When a 10 μF BP/M pin capacitor is used, the current limit is increased (I LIMITinc or I LIMIT +1), extending the power capability for applications requiring higher peak power or continuous power where the thermal conditions allow.Further ?exibility comes from the current limits between adjacent TinySwitch-III family members being compatible. The reduced current limit of a given device is equal to the standard current limit of the next smaller device and the increased current limit is equal to the standard current limit of the next larger device.
Key Application Considerations
TinySwitch-lll Design Considerations
Output Power Table
The data sheet output power table (Table 1) represents the minimum practical continuous output power level that can be obtained under the following assumed conditions:
1. The minimum DC input voltage is 100 V or higher for 85 V AC input, or 220 V or higher for 230 V AC input or 115 V AC with a voltage doubler. The value of the input capacitance should be sized to meet these criteria for AC input designs.
2. Ef?ciency of 75%.
3. Minimum data sheet value of I 2f.
4. Transformer primary inductance tolerance of ±10%.
5. Re?ected output voltage (V OR ) of 135 V .
6. V oltage only output of 12 V with a fast PN recti?er diode.
7. Continuous conduction mode operation with transient K P * value of 0.25.
8. Increased current limit is selected for peak and open frame power columns and standard current limit for adapter columns.
9. The part is board mounted with SOURCE pins soldered to a suf?cient area of copper and/or a heatsink is used to keep the SOURCE pin temperature at or below 110 °C.10. Ambient temperature of 50 °C for open frame designs and 40 °C for sealed adapters.*Below a value of 1, K P is the ratio of ripple to peak primary current. To prevent reduced power capability due to premature termination of switching cycles a transient K P limit of ≥0.25 is recommended. This prevents the initial current limit (I INIT ) from being exceeded at MOSFET turn on.
For reference, Table 2 provides the minimum practical power delivered from each family member at the three selectable current limit values. This assumes open frame operation (not thermally limited) and otherwise the same conditions as listed above. These numbers are useful to identify the correct current limit to select for a given device and output power requirement.Overvoltage Protection
The output overvoltage protection provided by TinySwitch-III uses an internal latch that is triggered by a threshold current of approximately 5.5 mA into the BP/M pin. In addition to an internal ?lter, the BP/M pin capacitor forms an external ?lter providing noise immunity from inadvertent triggering. For the bypass capacitor to be effective as a high frequency ?lter, the capacitor should be located as close as possible to the SOURCE and BP/M pins of the device.
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For best performance of the OVP function, it is recommended
that a relatively high bias winding voltage is used, in the range of
15 V-30 V. This minimizes the error voltage on the bias winding
due to leakage inductance and also ensures adequate voltage
during no-load operation from which to supply the BP/M pin
for reduced no-load consumption.
Selecting the Zener diode voltage to be approximately 6 V
above the bias winding voltage (28 V for 22 V bias winding)
gives good OVP performance for most designs, but can be
adjusted to compensate for variations in leakage inductance.
Adding additional ?ltering can be achieved by inserting a low
value (10 ? to 47 ?) resistor in series with the bias winding
diode and/or the OVP Zener as shown by R7 and R3 in
Figure 14. The resistor in series with the OVP Zener also limits
the maximum current into the BP/M pin.
Reducing No-load Consumption
As TinySwitch-III is self-powered from the BP/M pin capacitor,
there is no need for an auxillary or bias winding to be provided
on the transformer for this purpose. T ypical no-load consumption
when self-powered is <150 mW at 265 V AC input. The addition
of a bias winding can reduce this down to <50 mW by supplying
the TinySwitch-III from the lower bias voltage and inhibiting the
internal high voltage current source. To achieve this, select the
value of the resistor (R8 in Figure 14) to provide the data sheet
DRAIN supply current. In practice, due to the reduction of the
bias voltage at low load, start with a value equal to 40% greater
than the data sheet maximum current, and then increase the value
of the resistor to give the lowest no-load consumption.
Audible Noise
The cycle skipping mode of operation used in TinySwitch-III
can generate audio frequency components in the transformer.
To limit this audible noise generation the transformer should
be designed such that the peak core ?ux density is below
3000 Gauss (300 mT). Following this guideline and using the
standard transformer production technique of dip varnishing
practically eliminates audible noise. Vacuum impregnation
of the transformer should not be used due to the high primary
capacitance and increased losses that result. Higher ?ux densities
are possible, however careful evaluation of the audible noise
performance should be made using production transformer
samples before approving the design.
Ceramic capacitors that use dielectrics such as Z5U, when used
in clamp circuits, may also generate audio noise. If this is the
case, try replacing them with a capacitor having a different
dielectric or construction, for example a ?lm type.
TinySwitch-lll Layout Considerations
Layout
See Figure 15 for a recommended circuit board layout for
TinySwitch-III.
Single Point Grounding
Use a single point ground connection from the input ?lter capacitor
to the area of copper connected to the SOURCE pins.
Bypass Capacitor (C
BP
)
The BP/M pin capacitor should be located as near as possible
to the BP/M and SOURCE pins.
Primary Loop Area
The area of the primary loop that connects the input ?lter
capacitor, transformer primary and TinySwitch-III together
should be kept as small as possible.
Primary Clamp Circuit
A clamp is used to limit peak voltage on the DRAIN pin at turn
off. This can be achieved by using an RCD clamp or a Zener
(~200 V) and diode clamp across the primary winding. In all
cases, to minimize EMI, care should be taken to minimize the
circuit path from the clamp components to the transformer and
TinySwitch-III.
Table 2. Minimum Practical Power at Three Selectable Current Limit Levels.
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Thermal Considerations
The four SOURCE pins are internally connected to the IC lead frame and provide the main path to remove heat from the device. Therefore all the SOURCE pins should be connected to a copper area underneath the TinySwitch-III to act not only as a single point ground, but also as a heatsink. As this area is connected to the quiet source node, this area should be maximized for good heatsinking. Similarly for axial output diodes, maximize the PCB area connected to the cathode.
Y-Capacitor
The placement of the Y-capacitor should be directly from the primary input ?lter capacitor positive terminal to the common/return terminal of the transformer secondary. Such a placement will route high magnitude common mode surge currents away from the TinySwitch-III device. Note – if an input π (C, L, C) EMI ?lter is used then the inductor in the ?lter should be placed between the negative terminals of the input ?lter capacitors.
Optocoupler
Place the optocoupler physically close to the TinySwitch-III to minimizing the primary-side trace lengths. Keep the high current, high voltage drain and clamp traces away from the optocoupler to prevent noise pick up.
Output Diode
For best performance, the area of the loop connecting the secondary winding, the output diode and the output ?lter capacitor, should be minimized. In addition, suf?cient copper area should be provided at the anode and cathode terminals of the diode for heatsinking. A larger area is preferred at the quiet cathode terminal. A large anode area can increase high frequency radiated EMI.
Figure 15. Recommended Circuit Board Layout for TinySwitch-III with Under-Voltage Lock Out Resistor.
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Quick Design Checklist
As with any power supply design, all TinySwitch-III designs
should be veri?ed on the bench to make sure that component
speci?cations are not exceeded under worst case conditions. The
following minimum set of tests is strongly recommended:
1. Maximum drain voltage – Verify that V
DS
does not exceed
650 V at highest input voltage and peak (overload) output
power. The 50 V margin to the 700 V BV
DSS
speci?cation
gives margin for design variation.
2. Maximum drain current – A t maximum ambient temperature,
maximum input voltage and peak output (overload) power,
verify drain current waveforms for any signs of transformer
saturation and excessive leading edge current spikes at
startup. Repeat under steady state conditions and verify that
the leading edge current spike event is below I
LIMIT(Min)
at the
end of the t
LEB(Min)
. Under all conditions, the maximum drain
current should be below the speci?ed absolute maximum
ratings.
3. Thermal Check – At speci?ed maximum output power,
minimum input voltage and maximum ambient temperature,
verify that the temperature speci?cations are not exceeded
for TinySwitch-III, transformer, output diode, and output
capacitors. Enough thermal margin should be allowed for
part-to-part variation of the R
DS(ON)
of TinySwitch-III as
speci?ed in the data sheet. Under low line, maximum power,
a maximum TinySwitch-III SOURCE pin temperature of
110 °C is recommended to allow for these variations.
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D a t a S h e e
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NOTES:
A. I S1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these conditions. Total device consumption at no-load is the sum of I S1 and I DSS2.B Since the output MOSFET is switching, it is dif?cult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BP/M pin current at 6.1 V.C. BP/M pin is not intended for sourcing supply current to external circuitry.
D. To ensure correct current limit it is recommended that nominal 0.1 μF / 1 μF / 10 μF capacitors are used. In addition, the BP/M capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization.
E. For current limit at other di/dt values, refer to Figure 23.
F. TNY274 does not set an increased current limit value, but with a 10 μF BP/M pin capacitor the current limit is the same as with a 1 μF BP/M pin capacitor (reduced current limit value).
G. This parameter is derived from characterization.
H. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the I LIMIT speci?cation. I. I DSS1 is the worst case OFF state leakage speci?cation at 80% of BV DSS and maximum operating junction
temperature. I DSS2 is a typical speci?cation under worst case application conditions (recti?ed 265 VAC) for no-load consumption calculations.J. Breakdown voltage may be checked against minimum BV DSS speci?cation by ramping the DRAIN pin voltage up to but not exceeding minimum BV DSS .
K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency).
Nominal BP/M
Pin Cap Value
Tolerance Relative to Nominal
Capacitor Value
Min MAX 0.1 μF -60%+100%1 μF -50%+100%10 μF
-50%
NA
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Figure 17. Duty Cycle Measurement.
Figure 18. Output Enable Timing.
Figure 16. General Test Circuit.
P I -4279-013006
Figure 19. Current Limit Envelope.
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Typical Performance Characteristics
Figure 20. Breakdown vs. Temperature.
1.11.0
0.9-50-25
25
50
75100125150
Junction Temperature (°C)
B r e a k d o w n V o l t a g e (N o r m a l i z e d t o 25 °
C )
P I -2213-01230
1
DRAIN Voltage (V)
D r a i n C u r r e n t (m A )
300250
200100501500
2
4
6
8
10
Figure 21. Frequency vs. Temperature.
Figure 22. Standard Current Limit vs. Temperature.
Figure 23. Current Limit vs. di/dt.
Figure 24. Output Characteristic.
Figure 25. C OSS vs. Drain Voltage.
1.4
1.21.00.80.60.40.201
2
3
4
Normalized di/dt
N o r m a l i z e d C u r r e n t L i m i t
Drain Voltage (V)
D r a i n C a p a c i t a n c e (p F )
P I -4083-082305
0100200300400500600
1
10
100
1000
10.80.60.40.20-50
50
100
150
Temperature (°C)
P I -4102-010906
1.2
S t a n d a r d C u r r e n t L i m i t (N o r m a l i z e d t o 25 °C )
1.2
1.00.80.60.40.20
-50-250255075100125
Junction Temperature (°C)
P I -4280-012306
O u t p u t F r e q u e n c y (N o r m a l i z e d t o 25 °C )
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Typical Performance Characteristics (cont.)
50
30
40
10
20
020*******
DRAIN Voltage (V)
P
o
w
e
r
(
m
W
)
1.2
1.0
0.8
0.6
0.4
0.2
-50-250255075100125
Junction Temperature (°C)
P
I
-
4
2
8
1
-
1
2
3
6
U
n
d
e
r
-
V
o
l
t
a
g
e
T
h
r
e
s
h
o
l
d
(
N
o
r
m
a
l
i
z
e
d
t
o
2
5
°
C
)
Figure 27. Under-Voltage Threshold vs. Temperature.
Figure 26. Drain Capacitance Power.