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ACT-SF2816N-26P7I中文资料

ACT-SF2816N-26P7I中文资料
ACT-SF2816N-26P7I中文资料

FEATURES

CIRCUIT TECHNOLOGY

https://www.sodocs.net/doc/dd13375171.html,

I

2 – 128K x 8 SRAMs & 2 – 512K x 8 Flash Die in One MCM

I Access Times of 25ns (SRAM) and 60ns (Flash) or 35ns (SRAM) and 70 or 90ns (Flash)

I Organized as 128K x 16 of SRAM and 512K x 16 of Flash Memory with Separate Data Buses

I Both Blocks of Memory are User Configurable as 512KX8 AND 1MX8 Respectively I Low Power CMOS

I Input and Output TTL Compatible Design I MIL-PRF-38534 Compliant MCMs Available

I Decoupling Capacitors and Multiple Grounds for Low Noise

I Industrial and Military Temperature Ranges I Industry Standard Pinouts

I

Packaging – Hermetic Ceramic

G 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,

Aeroflex code# "P3"

G 66 Pin, 1.08" x 1.08" x .185" PGA Type, With Shoulder, Aeroflex code# "P7"

G 68 Lead, .94" x .94" x .140" Single-Cavity Small Outline Gull Wing, Aeroflex code# "F18" (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint)

I

DESC SMD – TBD

FLASH MEMORY FEATURES

I

Sector Architecture (Each Die)

G 8 Equal Sectors of 64K bytes each

G Any combination of sectors can be erased with one

command sequence

I +5V Programing, +5V Supply

I Embedded Erase and Program Algorithms I Hardware and Software Write Protection I Internal Program Control Time.I

10,000 Erase / Program Cycles

Pin Description

FI/O 0-15Flash Data I/O SI/O 0-15SRAM Data I/O A 0–18Address Inputs FWE 1-2

Flash Write Enables

SWE 1-2SRAM Write Enables FCE 1-2Flash Chip Enables SCE 1-2

SRAM Chip Enables OE Output Enable NC Not Connected V CC Power Supply GND

Ground

128Kx8

FCE 2

OE A 0 – A 18

SI/O 0-7

SI/O 8-15

FI/O 0-7

FI/O 8-15

88

88FCE 1FWE 2FWE 1SWE 2SWE 1SCE 1SCE 2

Block Diagram – PGA Type Packages (P3 & P7) & CQFP (F18)

SRAM 128Kx8SRAM 512Kx8Flash 512Kx8Flash ACT–SF2816 High Speed Note: Programming information available upon request

128Kx16 SRAM / 512Kx16 FLASH

Multichip Module

Absolute Maximum Ratings

Symbol Rating Range Units T C Operating T emperature-55 to +125°C T STG Storage T emperature-65 to +150°C V G Maximum Signal Voltage to Ground-0.5 to +7V T L Maximum Lead T emperature (10 seconds)300°C

Parameter

Flash Data Retention10 Y ears

Flash Endurance (Write/Erase Cycles)10,000

Normal Operating Conditions

Symbol Parameter Minimum Maximum Units

V CC Power Supply Voltage+4.5+5.5V

V IH Input High Voltage+2.2V CC + 0.3V

V IL Input Low Voltage-0.5+0.8V

Capacitance

(V IN = 0V, f = 1MHz, T C = 25°C)

Symbol Parameter Maximum Units

C A

D A0 – A18 Capacitance 50pF

C OE OE Capacitance50pF

C WE1,2F/S Write Enable Capacitance20pF

C CE1,2F/S Chip Enable Capacitance20pF

C I/O I/O0 – I/O15 Capacitance20pF These parameters are guaranteed by design but not tested

DC Characteristics

(V CC = 5.0V, V SS = 0V, Tc = -55°C to +125°C, unless otherwise indicated)

Parameter Sym Conditions Min Max Units Input Leakage Current I LI V CC = Max, V IN=0to V CC10μA

Output Leakage Current I LO FCE = SCE = V IH, OE = V IH,

V OUT=0to V CC

10μA

SRAM Operating Supply Current x 16 Mode I CC x16SCE = V IL, OE = V IH, f = 5MHz, V CC =

Max, FCE = V IH

325mA

Standby Current I SB FCE = SCE = V IH, OE = V IH, f = 5MHz,

V CC = Max

40mA

SRAM Output Low Voltage V OL I OL = 8 mA, V CC = Min, FCE = V IH0.4V SRAM Output High Voltage V OH I OH = -4.0 mA, , V CC = Min, FCE = V IH 2.4V Flash Vcc Active Current for Read (1)I CC1FCE = V IL, OE = V IH, SCE = V IH130mA

Flash Vcc Active Current for Program or Erase (2)I CC2FCE = V

IL

, OE = V IH, SCE = V IH150mA

Flash Output Low Voltage V OL I OL = 8 mA, V CC = Min, SCE = V IH0.45V Flash Output High Voltage V OH I OH = -2.5 mA, , V CC = Min, SCE = V IH0.85 x V CC V Flash Low Vcc Lock Out Voltage V LKO 3.2V Notes: 1) The I CC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The frequency component typically is less than 2mA/MHz, with OE at V IH 2) I CC active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: V IL = 0.3V, V IH = V CC - 0.3V

SRAM AC Characteristics

(V CC = 5.0V, V SS= 0V, Tc= -55°C to +125°C) Read Cycle

Parameter Symbol

–025

Min Max

–035

Min Max

Units

Read Cycle Time t RC2535ns Address Access Time t AA2535ns Chip Select Access Time t ACE2535ns Output Hold from Address Change t OH00ns Output Enable to Output Valid t OE1520ns Chip Select to Output in Low Z * t CLZ33ns Output Enable to Output in Low Z * t OLZ00ns Chip Deselect to Output in High Z * t CHZ1220ns Output Disable to Output in High Z * t OHZ1220ns * Parameters guaranteed by design but not tested

Write Cycle

Parameter Symbol

–025

Min Max

–035

Min Max

Units

Write Cycle Time t WC2535ns Chip Select to End of Write t CW2025ns Address Valid to End of Write t AW2025ns Data Valid to End of Write t DW1520ns Write Pulse Width t WP2025ns Address Setup Time t AS00ns Output Active from End of Write * t OW00ns Write to Output in High Z * t WHZ1020ns Data Hold from Write Time t DH00ns Address Hold Time t AH00ns * Parameters guaranteed by design but not tested

Truth Table

Mode SCE OE SWE Data I/O Power Standby H X X High Z Standby Read L L H Data Out Active Output Disable L H H High Z Active Write L X L Data In Active

Flash AC Characteristics – Read Only Operations (Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Symbol

JEDEC Stand’d

–60

Min Max

–70

Min Max

–90

Min Max

Units

Read Cycle Time t AVAV t RC607090ns Address Access Time t AVQV t ACC607090ns Chip Enable Access Time t ELQV t CE607090ns Output Enable to Output Valid t GLQV t OE303535ns Chip Enable to Output High Z (1)t EHQZ t DF202020ns Output Enable High to Output High Z(1)t GHQZ t DF202020ns Output Hold from Address, CE or OE Change, Whichever is First t AXQX t OH000ns Note 1. Guaranteed by design, but not tested

Flash AC Characteristics – Write / Erase / Program Operations, FWE Controlled

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Symbol

JEDEC Stand’d

–60

Min Max

–70

Min Max

–90

Min Max

Units

Write Cycle Time t AVAC t WC607090ns Chip Enable Setup Time t ELWL t CE000ns Write Enable Pulse Width t WLWH t WP404545ns Address Setup Time t AVWL t AS000ns Data Setup Time t DVWH t DS404545ns Data Hold Time t WHDX t DH000ns Address Hold Time t WLAX t AH454545ns Write Enable Pulse Width High t WHWL t WPH202020ns Duration of Byte Programming Operation t WHWH114TYP14TYP14TYPμs Sector Erase Time t WHWH2303030Sec Read Recovery Time before Write t GHWL000μs Vcc Setup Time t VCE505050μs Chip Programming Time505050Sec Chip Enable Hold Time t OEH1101010ns Chip Erase Time t WHWH3120120120Sec 1. T oggle and Data Polling only.

Flash AC Characteristics – Write / Erase / Program Operations, FCE Controlled

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Symbol

JEDEC Stand’d

–60

Min Max

–70

Min Max

–90

Min Max

Units

Write Cycle Time t AVAC t WC607090ns Write Enable Setup Time t WLE L t WS000ns Chip Enable Pulse Width t ELEH t CP404545ns Address Setup Time t AVEL t AS000ns Data Setup Time t DVEH t DS404545ns Data Hold Time t EHDX t DH000ns Address Hold Time t ELAX t AH454545ns Chip Enable Pulse Width High t EHEL t CPH202020ns Duration of Byte Programming t WHWH114TYP14TYP14TYPμs Sector Erase Time t WHWH2303030Sec Read Recovery Time t GHEL000ns Chip Programming Time505050Sec Chip Erase Time t WHWH3120120120Sec

AC Waveforms for Flash Memory Read Operations

t OH

t CE

t OE

t ACC

t RC

t DF

Output Valid

High Z

High Z

Outputs

OE

FWE

FCE

Addresses

Addresses Stable

FWE

OE

FCE

Data

Addresses

5.0V

5555H PA

Data Polling

PA

D7

D OUT

PD

AOH

t WHWH 1

t OE

t RC

t CE

t DF

t OH

t AH

t AS

t DH

t WPH

t WP

t DS

t CE

t WC

Write/Erase/Program

Operation for Flash Memory, FWE Controlled

Notes:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at byte address.

3. D7 is the 0utput of the complement of the data written to the deviced.

4. Dout is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

t GHWL

AC Waveforms Chip/Sector

Erase Operations for Flash Memory

Data

Addresses

V CC

5555H

Data Polling t AH

FCE

t AS

FWE

5555H

5555H

SA

2AAAH

2AAAH

t GHWL

t WP

t WPH t DS

t DH t CE

t VCE

55H

AAH

80H

55H

10H/30H

AAH OE

Notes:

1. SA is the sector address for sector erase.

AC Waveforms for Data Polling

During Embedded Algorithm Operations for Flash Memory

t OE

t CH

t WHWH 1 or 2

t OE

t OH

t DF

t CE

t OEH

*

* DQ7=Valid Data (The device has completed the Embedded operation).

DQ0–DQ6=Invalid

DQ7

DQ7=Valid Data

DQ0–DQ6Valid Data

High Z

FCE

DQ7

OE

FWE

DQ0-DQ6

FWE

OE

FCE

Data

Addresses

5.0V

5555H PA

Data Polling

PA

D7

D OUT

PD

AOH

t WHWH 1

t AH

t AS

t DH

t CPH

t CP

t DS

t WS

t WC

t GHWL

Notes:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at byte address.

3. D7 is the 0utput of the complement of the data written to the device.

4. D OUT is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

Write/Erase/Program Operation for Flash Memory, FCE Controlled

Pin Numbers & Functions

66 Pins — PGA-Type

Pin #Function Pin #Function Pin #Function Pin #Function 1SI/O 818A 1235FI/O 952FWE 12SI/O 919Vcc 36FI/O 1053FCE 13SI/O 1020SCE 137A 654GND 4A 1321NC 38A 755FI/O 35A 1422SI/O 339NC 56FI/O 156A 1523SI/O 1540A 857FI/O 147A 1624SI/O 1441A 958FI/O 138A 1725SI/O 1342FI/O 059FI/O 129SI/O 026SI/O 1243FI/O 160A 010SI/O 127OE 44FI/O 261A 111SI/O 228A 1845V CC 62A 212SWE 229SWE 146FCE 263FI/O 713SCE 230SI/O 747FWE 264FI/O 614GND 31SI/O 648FI/O 1165FI/O 515SI/O 1132SI/O 549A 366

FI/O 4

16A 1033SI/O 450A 417

A 11

34

FI/O 8

51

A 5

All dimensions in inches

1.085 SQ 1.000.600TYP

1.000.100 TYP

.020.016

.100 TYP

.165MIN .160Pin 56

Pin 66

Pin 11

Pin 1

Bottom View (P7 & P3)

MAX MAX

.020.016

.100.025.185MAX Side View

(P7)

Side View

(P3)

.050 DIA .035

TYP

TYP TYP

TYP "P7" — 1.08" SQ PGA Type Package (with shoulders on Pins 1, 11, 56 & 66)

"P3" — 1.08" SQ PGA Type Package Standard (without shoulders )

.145MIN

Ordering Information

Model Number

DESC SMD Number

Speed

Package

ACT–SF2816N–26P3Q TBD 25(S) / 60(F) ns 1.08"sq PGA-T ype ACT–SF2816N–37P3Q TBD 35(S) / 70(F) ns 1.08"sq PGA-T ype ACT–SF2816N–39P3Q TBD 35(S) / 90(F) ns 1.08"sq PGA-T ype ACT–SF2816N–26P7Q TBD 25(S) / 60(F) ns 1.08"sq PGA-T ype ACT–SF2816N–37P7Q TBD 35(S) / 70(F) ns 1.08"sq PGA-T ype ACT–SF2816N–39P7Q TBD 35(S) / 90(F) ns 1.08"sq PGA-T ype ACT–SF2816N–26F18Q TBD 25(S) / 60(F) ns .94"sq CQFP ACT–SF2816N–37F18Q TBD 35(S) / 70(F) ns .94"sq CQFP ACT–SF2816N–39F18Q

TBD

35(S) / 90(F) ns

.94"sq CQFP

Note: (S) = Speed for SRAM, (F) = Speed for FLASH

Part Number Breakdown

ACT–S F 2816 N–26P7Q

Aeroflex Circuit Technology

Memory Type

SF = SRAM Flash Combo Module Memory Depth

Memory Width, Bits Memory Speed Code

Package Type & Size

C = Commercial Temp, 0°C to +70°C I = Industrial Temp, -40°C to +85°C T = Military Temp, -55°C to +125°C

M = Military T emp, -55°C to +125°C, Screening *Q = MIL-PRF-38534 Compliant / SMD

Screening

* Screened to the individual test methods of MIL-STD-883

Surface Mount Packages Thru-Hole Packages F18 = .94"SQ 68 Lead Dual-Cavity CQFP

P3 = 1.085"SQ PGA 66 Pins

with out shoulder P7 = 1.085"SQ PGA 66 Pins

with shoulder

26 = 25ns SRAM & 60ns FLASH 37 = 35ns SRAM & 70ns FLASH 39 = 35ns SRAM & 90ns FLASH

Options, N = none

2 = 2M SRAM, 8 = Locations Aeroflex Circuit Technology 35 South Service Road

Plainview New York 11830

Telephone: (516) 694-6700FAX: (516) 694-6715

Toll Free Inquiries: 1-(800) 843-1553

C I R C U I T T E C H N O L O G Y

Specifications subject to change without notice.

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