Development of a 24 ch TDC LSI for the ATLAS Muon Detector
Yasuo Arai1 and Tsuneo Emura2
1KEK, National High Energy Accelerator Research Organization,
Institute of Particle and Nuclear Studies, (email@example.com)
2Tokyo University of Agriculture and Technology
A prototype TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. The LSI was processed in a 0.3 µm CMOS Gate-Array technology. It contains full functionality required in the final TDC.
To get a high resolution around 300 ps, an asymmetric ring oscillator and a PLL circuit are used. All the I/O signals, which are active during measurement, have LVDS interfaces. A JTAG interface is used for boundary scan and internal register setup. All the memory and control bits have parity bits so that a SEU can be detected. Radiation tolerance for Gamma ray and Neutron are also confirmed.
ATLAS precision muon tracker (MDT) requires high-resolution, low-power and radiation-tolerant TDC LSIs (called AMT: ATLAS Muon TDC). Total number of TDC channels is about 370 kch.
To study basic circuit elements and radiation tolerance, a test element group chip (AMT-TEG) was fabricated in 1999 and reported in the last LEB workshop . After the success of the AMT-TEG chip, we have developed a prototype chip (AMT-1) which has full functionality for the experiment. Here we report about the design and test results of the AMT-1 chip. System tests with front-end chip, chamber and readout modules are being scheduled.
AMT-1 chip was processed in a 0.3 µm CMOS Gate-Array technology (Toshiba TC220G). It contains 24 input channels, 256 words level 1 buffer, 8 words trigger FIFO and 64 words readout FIFO. It also includes trigger-matching circuit, which selects data according to the trigger ID. The selected data are transferred through 40~80 Mbps serial lines with DS-Link protocol.
To get a high resolution and stable operation, an asymmetric ring oscillator and a Phase Locked Loop (PLL) circuit are used. All the input and output signals which are active during measurement has LVDS interfaces. A JTAG interface is used for boundary scan and internal register setup. Built-In Self-Test for memories is also activated through the JTAG interface. All the memory and control bits have parity bits so that a Single Event Upset can be detected.
Although the technology is gate-array, we have made intensive analog simulation and paid much attention to cell layout to achieve a sub-nano second timing resolution. Several macro cells are developed for time critical and analog parts. Careful floor planning are done to minimize route of the time critical signals.
Photograph of the AMT-1 chips is shown in Fig. 1. The chip is packaged in a 144-pin plastic QFP with 0.5
mm pin pitch and about 110k gates are used.
Fig. 1 Photograph of the AMT-1 chip. The die size is about
6 mm by 6 mm.
II. MDT F RONT-E ND E LECTRONICS Block diagram of the MDT front-end electronics is shown in Fig. 2. Three ASD (Amp-Shaper-Discri) chips  and one AMT chip are mounted on a small multi-layer printed circuit board (mezzanine board), which plugs into a MDT end plug PCB.
Two modes of operation will be provided in MDT measurement. In one mode the ASD output gives the time over threshold information, i.e. signal leading and trailing edge timing. The other mode measures leading edge time and charge. The Wilkinson ADC serves as a time slew correction and also provides diagnostics for monitoring chamber gas gain. It operates by creating a gate of ~20ns width at the leading edge of the signal, integrating charge onto a holding capacitor during the gate, and then running