P4C187L-12DMB中文资料

Document # SRAM111 REV B

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)– 10/12/15/20/25/35/45 ns (Commercial)– 12/15/20/25/35 /45 ns (Industrial)– 15/20/25/35/45/55/70/85 ns (Military)

Low Power Operation – 743 mW Active -10

– 660/770 mW Active for -12/15– 550/660 mW Active for -20/25 /35– 193/220 mW Standby (TTL Input)

– 83/110 mW Standby (CMOS Input) P4C187

– 5.5 mW Standby (CMOS Input) P4C 187L (Military)Single 5V±10% Power Supply

P4C187/P4C187L

ULTRA HIGH SPEED 64K x 1STATIC CMOS RAMS

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM DIP (P3, D3, C3)

LCC Pin configurations at end of datasheet.

Data Retention with 2.0V Supply (P4C187L Military)

Separate Data I/O Three-State Output TTL Compatible Output Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved)– 22-Pin 300 mil DIP – 24-Pin 300 mil SOJ

– 22-Pin 290x490 mil LCC – 28-Pin 350x550 mil LCC

DESCRIPTION

The P4C187/P4C187L are 65, 536-bit ultra high speed static RAMs organized as 64K x 1. The CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V ± 10%tolerance power supply. Data integrity is maintained for sup-ply voltages down to 2.0V, typically drawing 10μA.Access times as fast as 10 nanoseconds are available,greatly enhancing system speeds. CMOS reduces power

consumption to a low 743mW active, 193/83mW standby for TTL/CMOS inputs and only 5.5 mW standby for the P4C187L.

The P4C187/P4C187L are available in 22-pin 300 mil DIP,24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-viding excellent board level densities.

P4C187/187L

MAXIMUM RATINGS (1)

Symbol Parameter Value Unit V CC

Power Supply Pin with –0.5 to +7V

Respect to GND Terminal Voltage with –0.5 to V TERM Respect to GND V CC +0.5V (up to 7.0V)

T A

Operating Temperature

–55 to +125

°C

Symbol Parameter Value Unit T BIAS Temperature Under –55 to +125°C Bias

T STG Storage Temperature –65 to +150

°C P T Power Dissipation 1.0W I OUT

DC Output Current

50

mA

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

I SB

Standby Power Supply Current (TTL Input Levels)CE ≥ V IH Mil.V CC = Max ., Ind./Com’l.

f = Max., Outputs Open ______4035____________

2015

40n/a 1.0n/a

mA

mA

______

CE ≥ V HC Mil.V CC = Max., Ind./Com’l.f = 0, Outputs Open V IN ≤ V LC or V IN ≥ V HC

Standby Power Supply Current

(CMOS Input Levels)

I SB1

Grade(2)Ambient Temperature

GND V CC

0V 0V

5.0V ± 10%5.0V ± 10%

0V 5.0V ± 10%–55°C to +125°C Symbol C IN C OUT

Parameter Input Capacitance Output Capacitance

Conditions V IN = 0V V OUT = 0V

57

Unit pF pF

CAPACITANCES (4)

V CC = 5.0V, T A = 25°C, f = 1.0MHz n/a = Not Applicable

Symbol DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage (2)V IH V IL V HC V LC V CD V OL V OH I LI I LO Parameter

Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage

Input Clamp Diode Voltage Output Low Voltage (TTL Load)

Output High Voltage (TTL Load)

Input Leakage Current Output Leakage Current

Test Conditions

V CC = Min., I IN = 18 mA I OL = +8 mA, V CC = Min.I OH = –4 mA, V CC = Min.V CC = Max. Mil.V IN = GND to V CC Com’l.V CC = Max., CE = V IH , Mil.V OUT = GND to V CC Com’l.

P4C187Min 2.2–0.5(3)V CC –0.2–0.5(3)

2.4–10–5–10–5Max V CC +0.50.8V CC +0.50.2–1.20.4

+10+5+10+5P4C187L

Min Max 2.2–0.5(3)V CC –0.2–0.5(3)

2.4–5

n/a –5n/a V CC +0.50.8V CC +0.5

0.20.4

–1.2+5n/a +5n/a Unit

V V V V V V V μA μA Notes:

1.Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability.

2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow.

3.Transient inputs with V IL and I IL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns.

4.This parameter is sampled and not 100% tested.

https://www.sodocs.net/doc/ad5553679.html,itary

Industrial

–40°C to +85°C 0°C to +70°C Commercial

*V CC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = V IL .

DATA RETENTION CHARACTERISTICS (P4C187L Military Temperature Only)

Symbol V DR I CCDR t CDR t R ?

Parameter

V CC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time

Test Conditons CE ≥ V CC –0.2V,V IN ≥ V CC –0.2V or V IN ≤ 0.2V

Min 2.0

0t RC §

Typ.*V CC = 2.0V 3.0V Max V CC = 2.0V 3.0V

Unit 1015600900V

μA ns ns

*T A = +25°C

§t RC = Read Cycle Time

?

This parameter is guaranteed but not tested.

DATA RETENTION WAVEFORM

I CC

Symbol Parameter

Temperature Range

Dynamic Operating Current*

Commercial Industrial Military

–10N/A

–12–15–20–25–35–45Unit N/A mA mA mA

POWER DISSIPATION CHARACTERISTICS VS. SPEED

N/A 150155160170180N/A

170

160

155

150

145

180170160155150N/A N/A –85N/A 145

N/A –70N/A 145

N/A –55N/A 145

N/A

P4C187/187L

Notes:

5.CE is LOW and WE is HIGH for READ cycle.

6.WE is HIGH, and address must be valid prior to or coincident with CE transition LOW.

7.Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested.

8.Read Cycle Time is measured from the last valid address to the first transitioning address.

TIMING WAVEFORM OF READ CYCLE NO. 2(6)

TIMING WAVEFORM OF READ CYCLE NO. 1(5)

AC CHARACTERISTICS—READ CYCLE

(V CC = 5V ± 10%, All Temperature Ranges)

(2)

Notes:

9.CE and WE must be LOW for WRITE cycle.

10.If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state.

11.Write Cycle Time is measured from the last valid address to the first

transition address.

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(9)

AC CHARACTERISTICS - WRITE CYCLE

(V CC = 5V ± 10%, All Temperature Ranges)

(2)

P4C187/187L

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9)

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test fixture.

Note:

Due to the ultra-high speed of the P4C187/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 μF high frequency capacitor is also required between V CC

and ground. To avoid signal reflections,

proper termination must be used; for example, a 50? test environment should be terminated into a 50? load with 1.73V (Thevenin Voltage) at the comparator input, and a 116? resistor must be used in series with D OUT to match 166? (Thevenin Resistance).

AC TEST CONDITIONS

TRUTH TABLE

Input Pulse Levels GND to 3.0V

Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V

Output Load

See Figures 1 and 2

Mode CE WE Output Power Standby H X High Z Standby Read L H D OUT Active Write

L

L

High Z

Active

P4C187/187L

ORDERING INFORMATION

SELECTION GUIDE

The P4C187 is available in the following temperature, speed and package options. The P4C187L is only available over the military temperature range.

* Military temperature range with MIL-STD-883, Class B processing.

N/A = Not Available

CERDIP DUAL IN-LINE PACKAGE

P4C187/187L

SOJ SMALL OUTLINE IC PACKAGE

RECTANGULAR LEADLESS CHIP CARRIER

PLASTIC DUAL IN-LINE PACKAGE

P4C187/187L

REVISIONS

DOCUMENT NUMBER:SRAM111

DOCUMENT TITLE:P4C187 / P4C187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS

REV.ISSUE

DATE

ORIG. OF

CHANGE

DESCRIPTION OF CHANGE

OR1997DAB New Data Sheet

A Oct-05JD

B Change logo to Pyramid

B Apr-07JDB Added 55, 70, and 85 ns speeds 元器件交易网https://www.sodocs.net/doc/ad5553679.html,