PT8528_v1.0
PowerView Technology Inc.
PT8528
Video Display Controller for
Security DVR
Premierely Data Sheet
Rev. 1.0
2008/02/18
PowerView Technology Inc. All Rights Reserved.
This information contained herein is the exclusive property of PowerView and shall not be distributed, reproduced, or disclosed in whole or in part without permission of PowerView.
Table of Contents
1. General Description - 4 -
1.1. Features.................................................................................................................................................- 4 -
1.2. Application............................................................................................................................................- 6 -
1.3. Block Diagram......................................................................................................................................- 7 -
2. Package Type and Pin Description - 8 -
2.1. Pin Configuration..................................................................................................................................- 8 -
2.2. Pin Assignment....................................................................................................................................- 10 -
3. Function Description - 14 -
3.1 Register Page Definition.......................................................................................................................- 14 -
3.2 System Register Definition...................................................................................................................- 15 -
3.2.1 System Control - 15 -
3.2.2 Spread Spectrum PLL - 16 -
3.2.3 PLL1/2 - 17 -
3.2.4 Multi-Function I/O Definition - 19 -
3.2.5 GPIO REGISTER Setting - 20 -
3.3 Sync processor(VGA-input).................................................................................................................- 22 -
3.4 DAC setting..........................................................................................................................................- 23 -
3.5 Data input.............................................................................................................................................- 24 -
3.5.1 video data, control signal mux, data control - 24 -
3.5.2 timing reference - 25 -
3.5.3 resolution detect - 27 -
3.5.4 interrupt setting - 28 -
3.6 De-interlace..........................................................................................................................................- 29 -
3.6.1 De_Interlace Control Register - 29 -
3.6.2 Motion Detection Control Register - 30 -
3.6.3 Temporal Noise Reduction Register - 31 -
3.6.4 HV Sync Output Control register - 32 -
3.6.5 Frame Rate Conversion Control register - 33 -
3.6.6 HV Skip Mode (Down Scaling Mode) Control register - 33 -
3.6.7 SDR SDRAM Control register - 34 -
3.6.8 SDR SDRAM Clock Control register - 35 -
3.7 Scaler....................................................................................................................................................- 36 -
3.7.1 Scaler Function Block - 36 -
3.7.2 Scaler Top Control Register - 37 -
3.7.3 Vsyn Input and Output Delay Timing Control Register - 38 -
3.7.4 Panel Output Hsync and Vsync Register - 38 -
3.7.5 Internal Video Test Pattern Register - 39 -
3.7.6 Scaling Ratio Register - 39 -
3.7.7 Scaling Input & Output Timing Status - 40 -
3.8 BCA......................................................................................................................................................- 44 -
3.8.1 Luminance Adjustment - 45 -
3.8.2 Color Adjustment - 46 -
3.8.3 Color Space Conversion - 48 -
3.9 Gain and Offset....................................................................................................................................- 50 -
3.10 OSD....................................................................................................................................................- 51 -
3.10.1 Display RAM - 51 -
3.10.2 User Define Font RAM (UDF) - 52 -
3.10.3 Color Look-Up Table (CLUT) - 53 -
3.10.4 Register - 56 -
3.11 Output Processor................................................................................................................................- 60 -
3.11.1 Gamma Correction - 60 -
3.11.2 Dither - 61 -
3.11.3 Output Reformat(for TTL output only) - 62 -
3.12 MCU...................................................................................................................................................- 63 -
3.12.0 Internal MCU MODE - 63 -
3.12.1 EXternal MCU MODE - 63 -
3.12.2 RAM - 63 -
3.12.3 Flash Memory - 63 -
3.12.4 Timer0, Timer1, Timer2, UART, INT0, INT1, INT2, INT3 interrupt - 63 -
3.12.5 Slave I2C - 64 -
3.12.6 Remote Control - 66 -
3.12.7 PWM - 67 -
3.12.8 Key-Scan ADC - 68 -
3.12.9 Interrupt 1/2/3 - 69 -
3.12.10 Watchdog - 71 -
3.12.11 Flash-EEPROM - 72 -
3.12.12 Slave IIC for external MCU mode - 73 -
3.12.13 SP/ICE - 73 -
4. I/O PAD - 74 -
4.1 Recommended Operating Conditions...................................................................................................- 74 -
4.2 DC characteristics.................................................................................................................................- 74 -
4.2 GPIO type.............................................................................................................................................- 75 -
5. DAC characteristics - 77 -
5.1 DC characteristics.................................................................................................................................- 77 -
5.2 TypicAL APPLICATION....................................................................................................................- 77 -
6. Package Outline - 78 -
1. General Description
1.1. Features
?Video input port
- Supports ITU-BT.601/656 interface (8-bit)
- Support 720x480i and 720x576i input resolution
?Video output
- Analog RGB
- 24-bit digital RGB (TTL)
- Triple 10-bit DACs output RGB signals to CRT or LCD monitor
- Support 640x480/800x600/1024x768/1280x1024/1440x900/1600x1050/1600x1200
- Output is synchronized to VGA Hsync and Vsync inputs
?Output Frame Rates
- 50Hz ~85Hz programmable
?3D Motion Adaptive De-interlacing
- Directional spatial filter to obtain smooth edge
- Only one 1x16Mb SDRAM is required
- When 3D de-interlacing, FRC, and 3D noise reduction are all disabled, SDRAM is not required and only 2D de-interlacing is performed
?3D Noise Reduction
?High Quality Scaling Engine
- Programmable horizontal and vertical zoom ratio
- Independent H/V scaling
- Supports PIP(with external switch)
?Color Management
- Programmable color space conversion
- 6-axis hue adjustment
- Saturation adjustment
- Programmable flesh-tone adjustment
?Contrast and brightness adjustment
- Contrast adjustment with black/white level stretch
- Brightness adjustment
- Sharpness adjustment/Peaking filter
?OSD
- Character based OSD
- Font size: 16x18
- Font ROM : 512 single color fonts
- 2048*16 bits RAM, stores user define fonts(approximate 113(1-bit),56(2-bit),37(3-bit) UDF)
- 512*16 bits RAM, stores character attributes
- Foreground and background color: 64 colors look up table
- Programmable 1x, 2x, 3x and 4x for character width and height
- 2 programmable background windows
- Support blinking effect
- Support fade in/out effect
?Gamma Correction
- User programmable RGB 10-bit gamma table
?Built-in self test pattern generator
?MCU
- Built-in 8051 CPU
- Data memory : 512 bytes RAM
- Support external program memory with serial flash memory via 4-wire interface
- Can be disabled
?Low speed 8-bit ADC for keypad scanning
?PWM outputs (8-bit resolution)
?Two slave mode I2C interfaces, up to 400KHz
- Interface for ISP, ICE and other I2C master
- Interface for external MCU control
?Support Infra-Red remote control (RC-6 w/ rising/falling edge capture 16-bit counter) ?General purpose I/Os
?Crystal oscillator
- 24MHz
- Support clock output for external MCU
?Package type :
- 128/208 QFP
1.2. Application
CRT/LCD
Monitor
1.3. Block Diagram
Input Processor De-interlace
FRC
Noise-reduction Scaler Contrast/Sharpness/Brightness
Gain Offset OSD Gamma Dither 8051 MCU PWM KPADC
I2C
INT PLL1Xtal OSC PLL2
SSPLL VGA Sync-proc RGB Histogram Triple 10-bit DAC
2. Package Type and Pin Description
128-pin QFP for analog RGB output; 208-pin QFP for analog RGB and 24-bit TTL output
2.1. Pin Configuration
D D _C S S V D D _R D D _K P P A D C [0]P A D C [1]R Q [0]/P 10R Q [1]/P 11VDD_P S S _P N T O V D D _V S S _S S _K P H S V S C O M R S
E V R E
F O U V R E F I A V S A V D 3I O A V D 33A V S S I O A V D 33A V S S I O A V D 33A V S S V S S _D A V D D _D A V S S _P L L 2V D D _P L L 2L L 2_F I L T E R P C P D P H P V R Q [2]/P 12D D _P
B A R A S
C A S W E C S A [1]A [0]A [10]A [3]A [2]
S S _K P D D _C S S _C V S S _P L L 2V D D _P L L 2L L 2_F I L T E R E S E T B R D D _K P P A D C [0]P A D C [1]P A D C [2]P A D C [3]T T L O [8T T L O [9T T L O [0T T L O [1T T L O [2T T L O [3T T L O [4T T L O [5T T L O [6T T L O [7V S S _V D D _R Q [3]/P 13R Q [2]/P 12R Q [0]/P 10R Q [1]/P 11S S _P S S _P V D D _N T O V S S _V D D _T T L E [23T T L E [22T T L E [21T T L E [20T T L E [19T T L E [18T T L E [17T T L E [16V D D _V S S _V S S _H S V S C O M R S E V R E F O U V R E F I A V S A V D 3I O A V D 33A V S S I O A V D 33A V S S I O A V D 33A V S S V S S _D A V D D _D A P D P H P V P C O D E 0O D E 1A [5]
D D _P A [4]B A R A S C A S W
E C S A [1]A [0]A [10]A [3]A [2]
55 VDD_P P PAD
power(3.3V)
56 TTLE[16] I/O GPIO shared with TTL even(single pixel) output data 16
57 TTLE[17] I/O GPIO shared with TTL even(single pixel) output data 17
58 TTLE[18] I/O GPIO shared with TTL even(single pixel) output data 18
59 TTLE[19] I/O GPIO shared with TTL even(single pixel) output data 19
60 TTLE[20] I/O GPIO shared with TTL even(single pixel) output data 20
61 TTLE[21] I/O GPIO shared with TTL even(single pixel) output data 21
62 TTLE[22] I/O GPIO shared with TTL even(single pixel) output data 22
63 TTLE[23] I/O GPIO shared with TTL even(single pixel) output data 23
64 VSS_P G PAD ground
65 38 VSS_C G Core
ground
power(1.8V)
Core
66 39 VDD_C P
67 40 AHVDD P Bandgap
VDD(3.3V)
68 41 AVSS G Bandgap
Ground
69 42 VREFIN I DAC reference voltage input
70 43 VREFOUT O DAC reference voltage output
71 44 RSET I DAC Resistor control magnitude of full-scale video signal
72 45 COMP I DAC Compensation pin
73 46 AVSSR G Ground for R channel
74 47 AVD33R P R channel VDD(3.3V)
75 48 IOR O Analog RED signal output
76 49 AVSSG G Ground for G channel
77 50 AVD33G P G channel VDD(3.3V)
78 51 IOG O Analog GREEN signal output
79 52 AVSSB G Ground for B channel
80 53 AVD33B P B channel VDD(3.3V)
81 54 IOB O Analog BLUE signal output
82 55 VSS_DAC G Ground for DAC
83 56 VDD_DAC P DAC
VDD(1.8V)
84 57 VSS_P G PAD ground
85 58 PHS O
output
Hsync
86 59 PVS O
output
Vsync
87 60 PDE O Data Enable output
88 61 PCK O Pixel Clock output
power(3.3V)
PAD
89 62 VDD_P P
90 63 VSI I VGA Vsync input
91 64 HSI I VGA Hsync input
92 TTLO[0] I/O GPIO shared with TTL odd output data 0
93 TTLO[1] I/O GPIO shared with TTL odd output data 1
94 TTLO[2] I/O GPIO shared with TTL odd output data 2
95 TTLO[3] I/O GPIO shared with TTL odd output data 3
96 TTLO[4] I/O GPIO shared with TTL odd output data 4
97 TTLO[5] I/O GPIO shared with TTL odd output data 5
98 TTLO[6] I/O GPIO shared with TTL odd output data 6
99 TTLO[7] I/O GPIO shared with TTL odd output data 7
100 VSS_P G PAD ground
power(3.3V)
101 65 VDD_P P PAD
102 TTLO[8] I/O GPIO shared with TTL odd output data 8
103 TTLO[9] I/O GPIO shared with TTL odd output data 9
104 NC
105 TTLO[10] I/O GPIO shared with TTL odd output data 10
106 TTLO[11] I/O GPIO shared with TTL odd output data 11
107 TTLO[12] I/O GPIO shared with TTL odd output data 12
108 TTLO[13] I/O GPIO shared with TTL odd output data 13
109 TTLO[14] I/O GPIO shared with TTL odd output data 14
110 TTLO[15] I/O GPIO shared with TTL odd output data 15
111 VSS_P G PAD ground
112 TTLO[16] I/O GPIO shared with TTL odd output data 16
113 TTLO[17] I/O GPIO shared with TTL odd output data 17 114 TTLO[18] I/O GPIO shared with TTL odd output data 18 115 TTLO[19] I/O GPIO shared with TTL odd output data 19 116 TTLO[20] I/O GPIO shared with TTL odd output data 20 117 TTLO[21] I/O GPIO shared with TTL odd output data 21 118 TTLO[22] I/O GPIO shared with TTL odd output data 22 119 TTLO[23] I/O GPIO shared with TTL odd output data 23
power(3.3V)
PAD
120 VDD_P P
121 66 PWM[0] I/O GPIO shared with PWM0 output
122 67 PWM[1] I/O GPIO shared with PWM1 output
123 68 PWM[2] I/O GPIO shared with PWM2 output
124 69 PWM[3] I/O GPIO shared with PWM3 output
125 70 VSS_P G PAD ground
126 70 VSS_C G Core
ground
power(1.8V)
127 71 VDD_C P
Core
128 72 AVSS_PLL1 G PLL1
ground
129 73 PLL1_VCO O PLL1 loop filter
130 74 AVDD_PLL1 P PLL1
power(3.3V)
131 75 VSS_P G
PAD ground
132 76 SDQ[0] I/O SDRAM data 0
133 77 SDQ[1] I/O SDRAM data 1
134 78 SDQ[2] I/O SDRAM data 2
135 79 SDQ[3] I/O SDRAM data 3
136 80 SDQ[4] I/O SDRAM data 4
137 81 SDQ[5] I/O SDRAM data 5
138 82 SDQ[6] I/O SDRAM data 6
139 83 SDQ[7] I/O SDRAM data 7
power
140 84 VDD_P P
PAD
141 85 SDQ[15] I/O SDRAM data 15
142 86 SDQ[14] I/O SDRAM data 14
143 87 SDQ[13] I/O SDRAM data 13
144 88 SDQ[12] I/O SDRAM data 12
145 89 SDQ[11] I/O SDRAM data 11
146 90 SDQ[10] I/O SDRAM data 10
147 91 SDQ[9] I/O SDRAM data 9
148 92 SDQ[8] I/O SDRAM data 8
149 93 SDM O SDRAM Data Mask output
150 94 SCK O SDRAM Clock output
151 95 SCKE O SDRAM Clock enable output
152 96 VSS_P G
PAD ground
153 97 SA[9] O SDRAM address 9
154 98 SA[8] O SDRAM address 8
155 99 SA[7] O SDRAM address 7
156 100 SA[6] O SDRAM address 6
157
NC
~
166
167 101 SA[5] O SDRAM address 5
168 102 SA[4] O SDRAM address 4
PAD
power(3.3V)
169 103 VDD_P P
170 104 SWE O SDRAM Write Enable(active low)
171 105 SCAS O SDRAM Column address strobe(active low) 172 106 SRAS O SDRAM Row address strobe(active low) 173 107 SCS O SDRAM Chip select(active low)
174 108 SBA O SDRAM Bank address
175 109 SA[10] O SDRAM address 10
176 110 SA[0] O SDRAM address 0
177 111 SA[1] O SDRAM address 1
178 112 SA[2] O SDRAM address 2 179 113
SA[3] O SDRAM address 3 180 VSS_P G PAD ground 181 114
VSS_C G Core ground
182 115 VDD_C P Core power(1.8V) 183 116 AVSS_PLL2 G PLL2 ground 184 117 PLL2_VCO O PLL2 loop filter 185 118 AVDD_PLL2 P PLL2 power(3.3V) 186 119 VDD_KP P KPADC power 187 120 KPADC[0] I/O GPIO shared with Keypad ADC 0 input 188 121 KPADC[1] I/O GPIO shared with Keypad ADC 1 input 189 KPADC[2] I/O GPIO shared with Keypad ADC 2 input 190 KPADC[3] I/O GPIO shared with Keypad ADC 3 input 191 122 VSS_KP G KPADC ground 192 123 VSS_P G PAD ground
193 124 IRQ[0]/P10 I/O GPIO shared with IRQ0 interrupt input or 8051 P10 194 125 IRQ[1]/P11 I/O GPIO shared with IRQ1 interrupt input or 8051 P11 195 126 IRQ[2]/P12 I/O GPIO shared with IRQ2 interrupt input or 8051 P12
196 IRQ[3]/P13
I/O GPIO shared with IRQ3 interrupt input or 8051 P13 197 127 IR I/O GPIO shared with Remote control IR input 198 128 INTO I/O GPIO shared with Interrupt output when slave mode 199 1 RESETB I Reset input active low 200 2 MODE0 I 201 3 MODE1 I Internal MCU or IIC slave mode (include test mode) “00” External Flash; “01” Slave mode; “1x” Test mode 202 ~ 208
NC
3. Function Description 3.1 Register Page Definition
Index Function
0x0000~0x00FF Global system control 0x0100~0x01FF Main channel data input 0x0200~0x02FF Reserved
0x0300~0x03FF Scaler
0x0400~0x04FF Reserved
0x0500~0x05FF Reserved
0x0600~0x06FF Reserved
0x0700~0x07FF Reserved
0x0800~0x08FF Reserved
0x0900~0x09FF De-interlacer
0x0A00~0x0AFF Color adjust
0x0B00~0x0BFF Contrast and brightness 0x0C00~0x0CFF OSD control
0x0D00~0x0DFF Reserved
0x0E00~0x0EFF Reserved
0x0F00~0x0FFF DOUT
0x1000~0x10FF Reserved
0x1100~0x11FF Reserved
0x1200~0x12FF Reserved
0x1300~0x13FF MCU
0x1400~0x14FF Reserved
0x1500~0x15FF Reserved
0x1600~0x16FF OSD CLUT
0x1700~0x19FF Reserved
0x1A00~0x1AFF Reserved
0x1B00~0x1BFF Reserved
0x1C00~0x1DFF Reserved
0x1E00~0x1EFF Reserved
0x1F00~0x1FFF Reserved
0x2000~0x27FF OSD display RAM
0x3000~0x3FFF OSD user font RAM
0x4000~0x40FF Gamma table (R0)
0x4100~0x41FF Gamma table (R1)
0x4200~0x42FF Gamma table (G0)
0x4300~0x43FF Gamma table (G1)
0x4400~0x44FF Gamma table (B0)
0x4500~0x45FF Gamma table (B1)
0x4600~0x4FFF Reserved
0x5000~0x5FFF Reserved
0x6000~0x60FF Reserved
0x6100~0x6FFF Reserved
0x7000~0x73FF CPU RAM
0x7400~0x7FFF Reserved
0x8000~0xFFFF Reserved
3.2 System Register Definition
3.2.1 SYSTEM CONTROL
Page = 00H
Index Default R/W Bit Name Description
00H 32H R/W 7:0 REV_ID revision ID code
01H 0 R/W 3 OSC_OFF shut down system clock, resumes when wake-up event (index-2) occurs
clear and set OSC_OFF to generate a rising edge to enable function
0 R/W 2 DIS_RST_DF 1: Disable digital filter for system reset
0: Enable digital filter for system reset(default)
0 R/W 1 DIS_LVR_33 1:Disable 3.3V LVR
0: Enable 3.3V LVR(default)
0 R/W 0 DIS_LVR_18 1: Disable 1.8V LVR
0: Enable 1.8V LVR(default)
0 R/W 7 WAKE_EN_CKI wake-up enable for 656-CLK
02H
0 R/W 6 WAKE_EN_UART wake-up enable for UART
0 R/W 5 WAKE_EN_I2C[1]wake-up enable for ISP_I2C
0 R/W 4 WAKE_EN_I2C[0]wake-up enable for SLA_I2C
0 R/W 3 WAKE_EN_SYNC wake-up enable for VSYNC and HSYNC(from VGA)
0 R/W 2 WAKE_EN_ADC wake-up enable for keypad-ADC
0 R/W 1 WAKE_EN_IRQ wake-up enable for IRQ[3:0] input
0 R/W 0 WAKE_EN_IR wake-up enable for IR input
04H 0 R/W 7 RST_GLOBAL F/W global reset (automatically cleared)
0 R/W 6 RST_DI reset din module
0 R/W 5 RST_DINT reset de-interlace module
0 R/W 4 RST_SBS reset scaler module
0 R/W 3 RST_BCA reset BCA block module
0 R/W 2 RST_GOB reset gain offset module
0 R/W 1 RST_OSD reset OSD module
0 R/W 0 RST_DO reset DO/Reformat module
7:4 Reserved
05H
1 R/W 3 DEMODE_OFF select scaler demo_de as reformat rfmt_de input
1: Disable GOB/DO demo function
0: Enable GOB/DO demo function
2:0 Reserved
06H 0 R/W 7-5 Reserved
0 R/W 4 SBS_VCK1_INV Invert VCK1(input of scaler)
DIN_VCK1_SEL
0 R/W 3
De-interlace clock select “1” : 13.5MHz “0”: 27MHz
0 R/W 2 RFT_CK_INV Invert reformat clock
0 R/W 1 DI_VCKO_INV Invert VCK1(output of di)
0 R/W 0 VCKI_INV Invert VCKi(input of di)
07H 0 R/W 7:4 Reserved
0 R/W 3:0 DAC_DLY[3:0] DAC clock delay line
08H 0 R/W 7:4 PDE_DLY[3:0] PDE delay line
0 R/W 3:0 PCK_DLY[3:0] PCK delay line
09H 0 R/W 7:0 Reserved
0 R/W 7:5 Reserved
0AH
0 R/W 4 PCK act PDEn ”0”
”1” PCK output as ~PDE(for PIP switch use)
0 R/W 3 PVS_OEN PVS pad ”0” Output enable ”1” Output disable 0 R/W 2 PHS_OEN PHS pad ”0” Output enable ”1” Output disable 0 R/W 1 PDE_OEN PDE pad ”0” Output enable ”1” Output disable 0
R/W 0 PCK_OEN PCK pad ”0” Output enable ”1” Output disable 7:6
Reserved
0 R/W 5 FCLK_DS Flash clock driving strength “0”: 4mA;”1”:8mA 0 R/W 4 PDE_DS PDE driving strength “0”: 4mA;”1”:8mA 0 R/W 3 PCK_DS PCK driving strength
“0”: 4mA;”1”:8mA 0 R/W 2 SDR_DQ_DS SDRAM DQ(DM/CKE) driving strength “0”: 4mA;”1”:8mA 0
R/W
1
SDR_CLK_DS
SDRAM CLK driving strength
“0”: 4mA;”1”:8mA 0BH
0 R/W 0 SDR_ADR_DS SDRAM Addr(RAS/CAS/CS/BA..) driving strength
“0”: 2mA;”1”:4mA
3.2.2 SPREAD SPECTRUM PLL
Criteria:
z 1MHz < Fref(Fin/NI) < 6MHz
z
350MHz < Fosc((Fin/NI)*NF) < 600MHz z Fpll = Fref
z Fout = (Fin * NF) / (NI * NO)
SS-PLL Register Page = 00H
Index Default R/W Bit Name Description
10H
4H
R/W
4:2
SS_PRESCALE
VCO2 prescaler selection: 000: /2
100: /8 001: /3 101: /12 010: /4 110: /16 011: /6
111: /1
01H R/W 1:0 SS_FINSEL FIN clock source selection
00: CKIN
VCK1 (DI output)
01: REFCK
XTAL input
10: HSYNC HSYNC(VGA) 11: HS*NF2 HSYNC(VGA)*NF2
11H 0H R/W 7:4 SS_T modulation period (no. of "freq" period) 0H R/W 3:0 SS_STEPN Spreading step no.
example: SS_STEPN = 2, 2 up & 2 down spreading steps 12H
R/W
3
SS_TMODE
test mode selection 0: PLL
1: digital (when TESTB = 0)
1 R/W
2 SS_TESTB test control pin, normal high
0 R/W 1 SS_PD force output to ground and power down (PLL off) 1 R/W 0 SS_ONSS spread enable 13H 0H R/W 3:0 SS_DELTA step size for NF spreading 14H 02H R/W 7:0 SS_NI[7:0] dividing number of input divider
15H 00H R/W 1:0 SS_NI[9:8] note: SS_BYPASS = '0' & SS_ONSS = '1' before programming SS_NI 16H 02H R/W 7:0 SS_NF[7:0]
dividing number of feedback divider
17H 00H R/W 1:0 SS_NF[9:8] note: SS_BYPASS = '0' & SS_ONSS = '1' before programming SS_NF 18H 02H R/W 7:0 SS_NO[7:0]
dividing number of output divider
19H 00H R/W 1:0 SS_NO[9:8] note: SS_BYPASS = '0' & SS_ONSS = '1' before programming SS_NO 1AH 02H R/W 7:0 SS_NF2[7:0] dividing number of feedback divider II
1BH
00H
R/W
2:0
SS_NF2[10:8]
note: SS_BYPASS = '0' & SS_ONSS = '1' before programming SS_NF2
3.2.3 PLL1/2
Criteria:
z 1MHz < Fref(Fin/NI) < 6MHz
z 350MHz < Fosc((Fin/NI)*NF) < 600MHz z Fpll = Fref
z Fout = (Fin * NF) / (NI * NO)
PLL1/2 Register Page = 00H
Index Default R/W Bit Name
Description
20H 7:5
Reserved
R/W
4
PLL1_FINSEL
FIN clock source selection 0:Xtal(24MHz) 1: ITU656 Clock(27MHz)
0 R/W 3 PLL1_TMODE test control pin, normal low
1 R/W
2 PLL1_TESTB test control pin, normal high
0 R/W 1 PLL1_PD force output to ground and power down (PLL1 off)
1 R/W 0 PLL1_EN program NI NF NO enable
21H 02H R/W 7:0 PLL1_NI[7:0] dividing number of input divider
22H 00H R/W 1:0 PLL1_NI[9:8] note: PLL1_PD = '0' & set PLL1_EN = '1' before programming PLL1_NI 23H 02H R/W 7:0 PLL1_NF[7:0] dividing number of feedback divider
24H 00H R/W 1:0 PLL1_NF[9:8] note: PLL1_PD = '0' & set PLL1_ON = '1' before programming PLL1_NF 25H 02H R/W 7:0 PLL1_NO[7:0] dividing number of output divider
26H 00H R/W 1:0 PLL1_NO[9:8] note: PLL1_PD = '0' & set PLL1_ON = '1' before programming PLL1_NO 27H 7:0 Reserved
28H
7:5 Reserved
0 R/W 4 PLL2_FINSEL FIN clock source selection 0:Xtal(24MHz) 1: ITU656 Clock(27MHz)
1 R/W 3 PLL2_TMODE test control pin, normal low
0 R/W 2 PLL2_TESTB test control pin, normal high
1 R/W 1 PLL2_PD force output to ground and power down (PLL
2 off)
0 R/W 0 PLL2_EN program NI NF NO enable
29H 02H R/W 7:0 PLL2_NI[7:0] dividing number of input divider
2AH 00H R/W 1:0 PLL2_NI[9:8] note: PLL2_PD = '0' & set PLL2_EN = '1' before programming PLL2_NI 2BH 02H R/W 7:0 PLL2_NF[7:0] dividing number of feedback divider
2CH 00H R/W 1:0 PLL2_NF[9:8] note: PLL2_PD = '0' & set PLL2_EN = '1' before programming PLL2_NF 2DH 02H R/W 7:0 PLL2_NO[7:0] dividing number of output divider
2EH 00H R/W 1:0 PLL2_NO[9:8] note: PLL2_PD = '0' & set PLL2_EN = '1' before programming PLL2_NO
3.2.4 MULTI-FUNCTION I/O DEFINITION
func_A_sel func_A
func_B
Description
GPIO_UR[1:0] UART_TXD/RXD
GPIO_PWM[3:0]
PWM[3:0] GPIO_ADC[3:0] ADC_IN[3:0] When enable ADC,disable OEN/RHN..
GPIO_IRQ[3:0] EN_P1[3:0] P1[3:0]
IRQ[3:0] GPIO_INT[1:0]
IR/INT
GPIO_EVEN EVEN[23:0] GPIO_ODD
ODD[23:0]
3.2.5 GPIO REGISTER SETTING
Page = 00H
Index Default R/W Bit Name Description
1 GPIO_ACT_TX 1: PAD act as GPIO
30H 03H R/W
0: PAD act as UART_TX
0 GPIO_ACT_RX 1: PAD act as GPIO
0: PAD act as UART_RX
31H 0FH R/W 3:0 GPIO_ACT_PWM 1: PAD act as GPIO
0: PAD act as PWM[3:0]
32H 0FH R/W 3:0 GPIO_ACT_ADC 1: PAD act as GPIO
0: PAD act as ADC[3:0]
33H 0FH R/W 3:0 GPIO_ACT_IRQ 1: PAD act as GPIO
0: PAD act as IRQ[3:0]
1 GPIO_ACT_IR 1: PAD act as GPIO
34H 03H R/W
0: PAD act as IR
0 GPIO_ACT_INT 1: PAD act as GPIO
0: PAD act as INT
35H FFH R/W 7:0 GPIO_ACT_EH 1: PAD act as GPIO
0: PAD act as EVEN [23:16]
36H FFH R/W 7:0 GPIO_ACT_EM 1: PAD act as GPIO
0: PAD act as EVEN [15:8]
37H FFH R/W 7:0 GPIO_ACT_EL 1: PAD act as GPIO
0: PAD act as EVEN [7:0]
38H FFH R/W 7:0 GPIO_ACT_OH 1: PAD act as GPIO
0: PAD act as ODD [23:16]
39H FFH R/W 7:0 GPIO_ACT_OM 1: PAD act as GPIO
0: PAD act as ODD [15:8]
3AH FFH R/W 7:0 GPIO_ACT_OL 1: PAD act as GPIO
0: PAD act as ODD [7:0]
Index Default R/W Bit Name Description 40H 03H R/W
1 GPIO_OEN_TX Output enable for TXD PAD(active low)
0 GPIO_OEN_RX Output enable for RXD PAD(active low)
41H 0FH R/W 3:0 GPIO_OEN_PWM Output enable for PWM[3:0] PAD(active low)
enable for ADC[3:0] PAD(active low)
42H 0FH R/W 3:0 GPIO_OEN_ADC Output
43H 0FH R/W 3:0 GPIO_OEN_IRQ Output enable for IRQ[3:0] PAD(active low)
44H 03H R/W
1 GPIO_OEN_IR Output enable for IR PAD(active low)
0 GPIO_OEN_INT Output enable for INT PAD(active low)
45H FFH R/W 7:0 GPIO_OEN_EH Output enable for EVEN [23:16] PAD(active low) 46H FFH R/W 7:0 GPIO_OEN_EM Output enable for EVEN [15:8] PAD(active low)
enable for EVEN [7:0] PAD(active low) 47H FFH R/W 7:0 GPIO_OEN_EL Output
48H FFH R/W 7:0 GPIO_OEN_OH Output enable for ODD [23:16] PAD(active low) 49H FFH R/W 7:0 GPIO_OEN_OM Output enable for ODD [15:8] PAD(active low)
enable for ODD [7:0] PAD(active low)
4AH FFH R/W 7:0 GPIO_OEN_OL Output
Index Default R/W Bit Name Description
50H 03H R/W
1 GPIO_DATA_TX output data for TXD PAD
0 GPIO_DATA_RX output data for RXD PAD
51H 0FH R/W 3:0 GPIO_DATA_PWM output data for PWM[3:0] PAD
52H 0FH R/W 3:0 GPIO_DATA_ADC output data for ADC[3:0] PAD