PAS6301_DataSheet_V1.3
PAS6301 Data Sheet
Preliminary Version Issue No. 1.3
August 2006
Legal Information
Copyright
Copyright 2006 PMC-Sierra, Inc. All rights reserved.
The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, no part of this document may be reproduced or redistributed in any form without the express written consent of PMC-Sierra, Inc. PMC-PAS6301, Issue 1.3
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability,
performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data
resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage.
Trademarks
For a complete list of PMC-Sierra’s trademarks, see our web site at Other product and company names mentioned herein may be the trademarks of their respective owners. Revision History Issue No. Issue Date Details of Change 1.0 July 2006 Initial version. 1.1 July 2006 Power pins modified & power consumption table added 1.2 August 2006 Estimated power supply table was updated ith more data and the Reference Voltage was added 1.3 August 2006 Table 4-8 updated Table of Contents Legal Information (2) Copyright (2) Disclaimer (2) Trademarks (2) Revision History (2) Table of Contents (4) List of Figures (6) List of Tables (7) 1Introduction (8) 1.1Purpose (8) 1.2System Overview (11) 1.2.1System Examples (11) 1.2.2Software Solutions (13) 1.3Functional Overview (14) 1.4Block Diagram (15) 1.5Component Functional Overview (15) 1.5.1EPON Interface and MAC (16) 1.5.2Packet Processing Engine (19) 1.5.3UNI (21) 1.5.4CPU Subsystem (23) 1.5.5OAM Functions (25) 2Pin Assignments (26) 3Functional Description (42) 3.1Overview (42) 3.2EPON Interface and MAC (42) 3.2.1SERDES and CDR (42) 3.2.2LLID Bridge (43) 3.2.3FEC (45) 3.2.4Security and Encryption (45) 3.2.5MAC (46) 3.2.6EPON Gating (47) 3.2.7Optics Control Interface (48) 3.2.8Support of the Multi-point Control Protocol (MPCP) (49) 3.2.9EPON LED Unit (52) 3.3Packet Processing Engine (53) 3.3.1Packet Classifier (54) 3.3.2VLAN Processor (56) 3.3.3Rate Limiter (61) 3.3.4Packet Queue (61) 3.4User Network Interface (63) 3.4.110/100/1000 Ethernet MAC (63) 3.4.2Management Interface (MDIO/MDC) (63) 3.4.3UNI Port Auto-negotiation (64) 3.4.4UNI Port Statistics Counters (64) 3.4.5UNI Port Registers for Configuration (65) 3.4.6UNI LED Unit (65) 3.5CPU Subsystem (65) 3.5.1CPU (66) 3.5.2I2C Interface Serial Interface (66) 3.5.3System Bus and Memory Interfaces (67) 3.5.4UART (67) 3.5.5GPIO (68) 3.5.6EEPROM (68) 3.5.7JTAG (68) 3.5.8Clock Unit (68) 3.5.9Timers (69) 4Electrical Specifications (70) 4.1General Operation Conditions (70) 4.2Timing Waveforms (70) 4.3GMII Interface (71) 4.4MII and MDIO Interfaces (73) 4.5Packet Buffer SDRAM Interface (77) 4.6CPU Peripherals Interface (78) 5Mechanical Specifications (80) 5.1Package (80) 5.2Thermal Characteristics (81) Index (82) List of Figures Figure 1-1: Typical EPNET Network Topology (11) Figure 1-2: Basic ONU as a Front-end to a Single PC (12) Figure 1-3: Basic ONU Connected to a Home Network with a Residential Gateway (12) Figure 1-4: Outdoor ONU – Single Home (13) Figure 1-5: PAS6301 Block Diagram (15) Figure 1-6: EPON Interface and MAC Block Diagram (16) Figure 1-7: Packet Processing Engine Block Diagram (19) Figure 1-8: UNI Block Diagram (21) Figure 1-9: CPU Subsystem Block Diagram (23) Figure 3-1: PMC-Sierra GE-PON Switch Functionality (44) Figure 3-2: Timing for Uplink Transmission (47) Figure 3-3: PON Uplink Transmission (48) Figure 3-4: MPCP Gating Mechanism (51) Figure 3-5: Threshold-based Operation (52) Figure 3-6: Packet Classification Structure (56) Figure 3-7: VLAN Mapping for the OLT and the PAS6301 in Customer Mode (57) Figure 3-8: VLAN Mapping for the OLT and the PAS6301 in Nested Mode (58) Figure 3-9: VLAN Mapping for the OLT and the PAS6301 in Service Mode – Untagged Frames (59) Figure 3-10: VLAN Mapping for the OLT and the PAS6301 in Service Mode – Tagged Frames (60) Figure 3-11: VLAN Mapping for the OLT and the PAS6301 in Exchange Mode (61) Figure 3-12: PAS6301 Queue Structure (62) Figure 4-1: Input Constraints (70) Figure 4-2: Output Constraints (71) Figure 4-3: GMII Receive Timing Measurements (71) Figure 4-4: GMII Transmit Measurements (71) Figure 4-5: UNI MII Transmit Timing – Master or Slave (STA or PHY) Modes (73) Figure 4-6: UNI MII Receive Timing – Master or Slave (STA or PHY) Modes (73) Figure 4-7: Management Interface Timing (75) Figure 4-8: Management MII Transmit Timing (75) Figure 4-9: Management MII Receive Timing (76) Figure 5-1: PAS6301 Package (80) List of Tables Table 3-1: EPON LED Functions (53) Table 3-2: LED Signals (65) Table 3-3: GPIO (68) Table 4-1: GMII DC Specifications (72) Table 4-2: GMII AC Specifications (72) Table 4-3: MII and MDIO DC Specifications (73) Table 4-4: UNI MII AC Specifications – Master (STA) or Slave (PHY) Modes (74) Table 4-5: MDIO AC Specifications (75) Table 4-6: Management MII AC Specifications (76) Table 4-7: SDPQ SDRAM DC Specifications (77) Table 4-8: SDPQ SDRAM AC Specifications (77) Table 4-9: CPU Peripherals DC Specifications (78) Table 4-10: CPU Peripherals AC Specifications (79) Table 5-1: PAS6301 Package Markings (81) 1 Introduction This chapter provides a general description of the PAS6301 device. 1.1 Purpose The PAS6301 chip provides the core functionality of an 802.3ah Ethernet Passive Optical Network (EPON) Optical Network Unit (ONU) solution. The PAS6301 offers the functionality required in an EPON ONU device, including an integrated serializer/deserializer (SERDES) and an ARM922 processor. The device is targeted at Fiber-to-the-Home (FTTH) solutions and can also be used as the uplink physical layer (PHY) device in a Fiber-to-the-Cabinet solution. The PAS6301 is supplied with a complete software development platform and a board support package that enables developers to create a comprehensive ONU solution. The PAS6301 integrates the EPON Media Access Control (MAC) and a protocol management function, an advanced packet classification engine including an upgraded IP address and UDP/TCP classification engine, a 10/100/1000 Ethernet interface in the user interface, an A2D and an additional 10/100 Ethernet interface for switch management. The PAS6301 is the latest member in PMC-Sierra's family of ONU solutions after the PAS6201 device. It works in combination with PMC-Sierra's family of Optical Line Terminal (OLT) solutions, and also accommodates other Ethernet-in-the-First-Mile-compliant (EFM) OLT solutions. The PAS6301 has the following features: ?Based on IEEE 802.3ah EPON ONU functionality ?Advanced classification engine and support for Virtual Local Area Networks (VLANs), and video services with IP Multicast, IPv4 or IPv6 ?An upgraded classification engine supporting Layer 3 and Layer 4 (meaning IP address and UDP/TCP port) ? A cost-effective SDRAM-based packet buffer (both for upstream and downstream) with up to eight priority queues and up to 8 MB of bursty traffic protection for IPTV applications ?Advanced switch management capabilities, including a standard dedicated MII interface and an L2 software management package (STP, IGMP and so on) supporting external switches ? A glueless interface to an on-board limiting amplifier and laser diode driver providing a highly integrated and cost-effective solution ? A flexible rate limiting function allowing limiting traffic by priority queue, by VLAN ID, or by the total traffic, both for upstream and downstream ?Open software development platform with an integrated ARM922 controller ?Comprehensive ONU software package and development kit, with support for Linux, VxWorks and a small-footprint microkernel operating system ?Full management through an Operation Administration Management (OAM) protocol based on IEEE 802.3ah ?Flexible optical transceiver interface for multiple vendor support ?Forward Error Correction (FEC) coding for an improved link budget ?Advanced threshold and queue-level reporting that supports buffer threshold reporting for compatibility with dynamic threshold control Dynamic Bandwidth Allocation (DBA) algorithms ?Integrated SERDES and Clock Data Recovery (CDR) for loop timing support at PON interface ?Hardware accelerator for DBA operation and configuration that supports low packet latency ?Eight priority queues with multi-protocol classifier, including: o VLAN manipulation and QoS support o802.1p priority, IPv6 and IPv4 o IP address and TCP/UDP port (both source and destination) ?128-bit Advanced Encryption Standard (AES) encryption for both downstream and upstream directions ?Support for CTC technical requirements including a 24-bit triple churning encryption for downstream and a dedicated rate limiting mode for Multicast/Broadcast frames ?802.1x authentication engine with remote administration for device and user authentication ?802.3x flow control for the User Network Interface (UNI) with programmable threshold configuration ?802.1d and 802.1q bridging, including a 128-port local address table with a programmable aging mechanism for isolation of home traffic from the network ?Capability of management through a UART craft interface ? A variety of interfaces with the following features: o Full-duplex transmit and receive EPON port operating at 1.25 Gbps with an integrated SERDES o Full-duplex 10/100MII or 1000Mbps GMII Ethernet for connectivity to both standard Ethernet PHY devices and standard Ethernet switch devices o32-bit ARM922 CPU bus for peripheral access and SDRAM and FLASH memory access o Optional Electrical Erasable Programmable Read-only Memory (EEPROM) interface for storage of boot configuration parameters o OAM indication pins for dying gasp and additional vendor-specific signals o LED control lines for glueless interfacing o I2C Small Form-factor Pluggable (SFP) interface port o Two UART ports for debug and control by external devices ?Management software package that includes SNMP, Web-based management, and operator-specific OAM stacks (specific details for each software package are defined in the relevant software manuals) ?Conforms to the requirements of the Europeen Union Restriction on the use of Hazardous Substances (RoHS) Directive, 2002/95/EC 1.2 System Overview The PAS6301 is designed to be the main component in an ONU device. Figure 1.1 shows the topology of a typical EPON network: Figure 1.1: Typical EPNET Network Topology Examples 1.2.1 System The PAS6301 supports different types of ONU and CPE solutions that connect to an EPON network. In an FTTH solution, the PAS6301 operates as the ONU controller. On the network side, it provides a programmable interface to the optical transceiver. On the user side, it provides a flexible GMII/MII interface that supports any type of Ethernet connection, up to GbE speeds. The packet classification unit and packet buffer engine support all of the networking functions required in an EPON ONU. The integrated ARM922 CPU and the system development kit, which includes the operating system and device drivers, facilitates the development of a complete ONU solution that also supports additional third-party, on-board peripherals. The system examples that follow show two types of solutions that can be developed using the PAS6301 as the main control of an ONU. In Figure 1.2, the ONU is connected directly to the user's PC or home network. In Figure 1.3, a residential gateway is connected to the ONU and provides additional functionality to the home network, such as disk storage and video streaming. PON Figure 1.2: Basic ONU as a Front-end to a Single PC PON Figure 1.3: Basic ONU Connected to a Home Network with a Residential Gateway The PAS6301 can be used in combination with a V oice-over-IP (V oIP) processor to implement an outdoor or indoor ONU that supports both data and voice services, as illustrated in Figure 1.4. PON Outdoor Single Home VoIP ONU Figure 1.4: Outdoor ONU – Single Home In Multi Dwelling Unit (MDU) or FTTC solutions, the PAS6301 can be used to implement a pizza box solution with 12 to 48 fast Ethernet or VDSL ports. It can also be used in PHY mode serving as the slave of an external GMII/MII master. Solutions 1.2.2 Software An open development platform enables integration of PAS6301 drivers and modules together with a customer's application-specific software, in order to create each specific ONU solution. PAS6301 software and APIs are explained in separate software manuals and APIs. The PAS6301 provides two types of software: ?An integrated "shrink-wrapped" software solution with a microkernel for basic applications ? A platform for development of system software using VxWorks or Linux operating systems The advanced development platform solution requires extra memory and accommodates the development of advanced management functionality, as well as the addition of applications, such as V oIP to an ONU based on the PAS6301. 1.3 Functional Overview PAS6301 functionality can be divided into two primary functions: a data path function and a control plane function. The data path is composed of an EPON MAC and transceiver interface based on the IEEE 802.3ah standard, together with FEC functions and link encryption engines for both uplink and downlink traffic. A Multi-point Control Protocol (MPCP) engine synchronizes the upstream bursts of traffic, according to standard GATE messages that are received from the OLT. A Packet Classification engine performs VLAN manipulations, 802.1d/q bridging and QoS classifications, in order to support various Ethernet-based network topologies. Advanced priority queues and a flow control mechanism to the UNI support up to eight levels of QoS, as well as advanced DBA algorithms implemented in the OLT. The UNI is an 802.3 10/100/1000 Ethernet MAC. The control plane function is closely tied to the data path and performs all EPON ONU management functions, including OAM message processing and data path function management. This functionality is performed by the hardware blocks in the PAS6301 and by the software running on the PAS6301 embedded processor. This document describes the hardware blocks of the PAS6301. Software functionality is described in separate software documents. 1.4 Block Diagram Figure 1.5 presents a block diagram with the major blocks comprising the PAS6301 chip. The five functional groups comprising the chip are color-coded in the diagram for ease of reference. Refer to section 1.5 for details about each of these groups. Figure 1.5: PAS6301 Block Diagram 1.5 Component Functional Overview The sections that follow describe the four basic functional groups comprising the PAS6301 and their associated blocks, which are shown in the PAS6301 block diagram (see Figure 1.5). These functional groups are: ?EPON interface and MAC (shown in pink in Figure 1.5; see section 1.5.1) ?Packet processing engine (shown in blue in Figure 1.5; see section 1.5.2) ?UNI (shown in yellow in Figure 1.5; see section 1.5.3) ?CPU subsystem (shown in green in Figure 1.5; see section 1.5.4) ?Operation, administration and maintenance (shown in white in Figure 1.5; see section 1.5.5) Further explanations for each functional group and its components can be found in Chapter 3, Functional Description. 1.5.1 EPON Interface and MAC The EPON interface and MAC provide all required components and functionality for transmitting or receiving over an EPON link. Figure 1.6: EPON Interface and MAC Block Diagram This functional group consists of the following blocks: ?Media Access Control [MAC], as described on page 16 ?SERDES, as described on page 17 ?FEC, as described on page 17 ?Logical Link Identifier (LLID) Bridge, as described on page 17 ?Optics Control, as described on page 18 ?MPCP, as described on page 18 ?Security, as described on page 18 ?EPON LED unit (not shown in block diagram), as described on page 18 Each of these blocks is described in the sections that follow. MAC The third generation MAC function is based on the 802.3ah-standard and supports both point-to-multipoint and point-to-point operation modes. For upstream traffic, this block verifies that packets are transmitted successfully, and that the ONU is properly registered on the link for point-to-multipoint transmissions. It also reports its bandwidth requirements and transmits relevant packets (when granted) according to the EPON protocol. For the receive path, the MAC receives Ethernet packets from the OLT and accepts those packets destined to this specific ONU. This block includes a gating function that is controlled by the MPCP engine and enables transmission bursts. The MAC function generates and receives frames with a length of up to 1600 bytes. MAC functionality includes: ?Frame reception and transmission ?Framing and decoding of Ethernet MAC and MAC control frames, including Frame Check Sequence (FCS) generation and error detection (a packet is discarded when an FCS error is encountered) SERDES An integrated SERDES provides a serial interface that operates at 1.25 GHz using differential signaling, which connects to standard EPON transceivers. Clock recovery is performed in the SERDES. This timing reference is used for the operation of the ONU and for the uplink transmission according to the EPON protocol. Control of optical transceivers is performed with programmable signals that enable the transmission. They also report loss of signal. An I2C bus can be used to read the parameters of plug-in transceiver modules that conform to the SFP industry standard. FEC FEC encoding and decoding can be performed on the data flow. When FEC functionality is enabled, FEC is performed on the link, meaning error correction coding is applied to transmitted packets and corrupted packets received from the OLT or the network are corrected. This function increases the optical link budget by up to 4 dB and can be used to increase the number of optical splits or to increase performance over poor optical links. It is an optional function that can be enabled or disabled, as defined in the standard. The FEC function can receive both coded and un-coded packets. LLID Bridge The LLID Bridge performs point-to-point emulation, which is required when creating a point-to-multipoint Ethernet network. The ONU is assigned a single LLID during the discovery process. This LLID is unique within the EPON link and is used to identify every packet going to and from the ONU. Packets with the unique LLID of the ONU in the header are accepted in the ONU by the LLID Bridge when the Broadcast bit is clear, and rejected when the Broadcast bit is set. In addition, packets with a broadcast LLID are also accepted in the ONU. The LLID is attached to every packet transmitted by the ONU. Optics Control The Optics Control block supplies the control interface to the optical transceivers. This block provides the burst mode control signals required by optical transceivers in EPON ONU applications. It receives status indications from the optical transceiver, and supports a broad range of optical transceivers, which are connected to the ONU by two types of signals – data path signals (connected via the SERDES) and control signals. MPCP Engine The MPCP engine performs the functions required to maintain the point-to-multipoint link. A timestamp of the EPON network is maintained and extracted from messages received from the OLT. This timestamp is used to synchronize TDM access to the uplink transmission. The MPCP block is also responsible for the discovery process in which the ONU device performs its registration during time slots indicated by the OLT. Access to these time slots is based on a random delay algorithm, as defined in the standard. The MPCP function includes a queue status reporter that sends REPORT messages to the OLT as a response to GATE messages, which request the status of the uplink queue in the ONU. A threshold method for queue-level reporting is also supported, where queue levels, up to a configured threshold, can be reported. In this mode, which is designed to support specific DBA algorithms, each subsequent report does not include frames that were previously reported and only specifies additional frames that were added to the queues after the previous report. Security The PAS6301 implements an encryption function that can encrypt both downlink and uplink transmissions. Downlink encryption adds a security mechanism against eavesdropping. Upstream encryption verifies the source of information in a many-to-one EPON topology. The PAS6301 implements AES-128 and 24-bit triple churning, which are required in some operating systems. The default state of the PAS6301 is without encryption. OLT authentication of the ONU is an important function in a point-to-multipoint system. The ONU can create and receive 802.1x messages, as well as other authentication methods that use OAM messages. This function is performed by the software, which transmits and receives the authentication messages through the EPON-to-CPU queues. EPON LED Unit The PAS6301 has four LED outputs to indicate its EPON activity status. The unit generates LED-driving lines indicating the status of the ONU and the EPON port. 1.5.2 Packet Processing Engine The PAS6301’s packet processing engine functional group serves as a bridge between the EPON protocol and the Ethernet protocol. This group is subdivided into two data paths – one for upstream traffic and one for downstream traffic. Figure 1.7: Packet Processing Engine Block Diagram Both upstream and downstream data paths are comprised of identical blocks, which are: ?Packet Classifier, as described on page 19 ?Rate Limiter, as described on page 20 ?VLAN Processor, as described on page 20 ?Packet Queue, as described on page 21 ?Packet Buffer Memory Controller, as described on page 21 The packet processing engine has additional interfaces beyond those used for the upstream and downstream data paths. An interface to external memory is available that serves as a packet buffer. There are also interfaces to the CPU through specific packet queues, including the PON Queue interface and the UNI Queue interface. Each of the blocks comprising the packet processing engine is described in the sections that follow. Packet Classifier The Packet Classifier, together with the VLAN function, determines the destination of a packet (CPU, data interface or discard), as well as the priority of the packet in the queues. The uplink Packet Classifier has an address table with an aging mechanism that can learn up to 128 source addresses (SAs). Only packets with a destination address (DA) that does not appear in the address table are forwarded to the uplink queue. The PAS6301 has a configured self-MAC address that identifies packets going to and from the CPU. The Ethertype field is used to create packet-forwarding decisions and determine if the VLAN module must process the packet. The IP field is used to identify IGMP or other protocols’ packets to be processed by the firmware. The IP source address, IP destination address, UDP/TCP source port and UDP/TCP destination ports fields can also be used for classification activities. Rate Limiter Uplink and downlink rate limiting can be performed by the PAS6301 on a per-queue, per VLAN ID, or per-the-total-traffic basis. The rate limiting function has a “leaky bucket” mechanism and also a burst size limiting mechanism. In the leaky bucket rate limiter, the sustainable rate can be configured in multiples of 100 Kbps. The maximum burst size (measured in consecutive bytes) can also be configured so that traffic exceeding this limit is discarded. VLAN Processor The PAS6301 VLAN processor performs VLAN header manipulation to accommodate network VLAN functionality. The VLAN function can identify and filter up to eight VLANs. Priority information is taken from the VLAN Priority bits, the ToS field of the IPv4 header, or the IPv6 Priority bits. The VLAN engine uses these fields to determine the VLAN processing function to be performed on the packet and to which queue to forward the packet. The VLAN engine supports 802.1q VLAN bridging, and can operate with the following capabilities: ?Transparent VLAN operation – In this case, the function ignores user-inserted VLAN tags, should they exist. ?Multicast group VLAN mode – This mode permits a group of ONUs to belong to a VLAN. In this mode, the VLAN function enables packets with a VLAN tag configured by the management system to pass through the ONU. The VLAN function does not add or remove the VLAN tag. ?Nested VLAN tag mode – This mode supports the creation of VLAN groups over the PON network and customer network VLAN tagging. In this case, an additional VLAN tag is added to the packet in the uplink direction and removed in the downlink direction. Priority information can be taken from IPv4/IPv6 or VLAN Priority fields. ?VLAN tag exchange mode – This mode exchanges a user VLAN with an EPON network VLAN. Priority information can be taken from IPv4/IPv6 or VLAN Priority fields.