A Scalable Architecture for Dual Basis GF(2m) Multiplications

A Scalable Architecture for Dual Basis GF(2m)

Multiplications

Liang-Hwa Chen??,Po-Lun Chang?,

?Department of Computer Information

and Network Engineering,

?Department of Electrical Engineering, Lunghwa University of Science and Technology,

Taoyuan,Taiwan

?Email:whallis2000@https://www.sodocs.net/doc/4e3733535.html,.tw

Yen-Ching Chang§,Chiou-Yng Lee??

§School of Applied Information Sciences, Chung Shan Medical University,

Taichung,Taiwan

??Department of Computer Information

and Network Engineering, Lunghwa University of Science and Technology,

Taoyuan,Taiwan

Abstract—A novel low-complexity scalable architecture for dual basis multiplications over GF(2m)is proposed in this paper. This multiplier architecture is derived from the Hankel matrix-vector representation of dual basis multiplication,and is feasible for the?nite?elds generated by irreducible trinomials.By appro-priately selecting its digit size,the proposed scalable architecture can achieve a satisfactory trade-o?between hardware complexity and throughput performance for implementing ECC cryptosys-tems such as ECDSA in resource-constrained environments such as embedded systems and smart cards.Analytical results exhibit that the space complexity of the proposed multiplier architecture is substantially lower than that of the non-scalable architectures. Besides,owing to its features of regularity,modularity and concurrency,the proposed architecture is highly feasible for VLSI implementations.

Keywords-Finite?eld,Dual basis,Hankel matrix-vector,Scal-able multiplier,Elliptic curve cryptography(ECC)

I.I ntroduction

In recent years,mobile communications and Internet trans-actions have become more and more popular,leading to increasing concern over the issue about integrity of transmitted data,against eavesdropping or unauthorized data altering.The advances in cryptography research thus have received increas-ing interest as well[1].Cryptography frequently involve?nite ?eld arithmetic operations,especially for the binary extension ?eld GF(2m).In particular,the elliptic curve cryptography (ECC)[2],which has become increasingly popular owing to its ability to realize a robust cryptosystem in smart cards,mobile phones and other resource-constrained environments,requires ?nite?eld arithmetic operations.The National Institute for Standards and Technology(NIST)has recommended the el-liptic curve digital signature algorithm(ECDSA)standard[3], in which?ve GF(2m),i.e.for m=163,233,283,409and571, are used to achieve adequate security.Among the basic arithmetic operations over GF(2m),multiplication is the most important and time-consuming computation.Other complex arithmetic operations,including exponentiation,division and multiplicative inversion,can be performed by repeating mul-tiplications,subsequently explaining the high demand for ef-?cient design and implementation of the?nite?eld multiplier with a low complexity.

For?nite?eld GF(2m),three conventionally adopted bases are polynomial basis(PB),normal basis(NB)and dual basis (DB)to represent its elements.Each representation has its own distinct advantages.For instance,the polynomial basis multi-plier does not require basis conversion and is characterized by its regularity and simplicity.The normal basis multiplier is quite e?ective in performing squaring an element in the?nite ?eld.The dual basis multiplier needs the least number of gates that leads to the smallest chip area demand for VLSI imple-mentation[4].Pertinent literature in recent years has generally classi?ed most?nite?eld multipliers on these bases as bit-serial[5]and bit-parallel architectures[6],[7].Cryptography applications such as the above-mentioned ECDSA heavily rely on?nite?elds of large values of m(160or higher)to achieve a su?cient level of security.To implement such cryptosystems, although the bit-serial architecture requires less chip area,its throughput is too slow.Conversely,the bit-parallel architecture is typically faster yet more complex and requires a signif-icantly larger chip area and power consumption.Digit-serial architectures[8],[9]have been proposed to facilitate the trade-o?between throughput performance and hardware complexity. These architectures are based on a cut-set systolization scheme to accelerate the computational process.However,such an architecture has a space complexity similar to that of the original bit-level multiplier design,making it infeasible for implementing cryptosystems that require a large number of operand bits in resource-constrained environments.Scalable architectures[10],[11]have subsequently been developed to satisfy the demands for implementing ECC cryptosystems such as ECDSA in resource-constrained environments.As a combination of serial and parallel schemes,the scalable architecture requires smaller chip area than that of the digit-serial architecture.In the scalable architecture,each m-bit operand word in the GF(2m)?eld is separated into k= m/d d-bit sub-words which are also termed as digits.Two operand words are multiplied in digits with a serial scheme while two digits are multiplied with a parallel scheme.Digit size d is normally selected to be substantially smaller than the operand bit length m.Thus,a substantially smaller hardware area multiplier(for d-bit operands)that can be easily implemented

2012 International Symposium on Biometrics and Security Technologies

in resource-constrained environments is su ?cient to perform all of the m -bit multiplications.Additionally,considering the trade-o ?between throughput performance and hardware complexity allows the scalable architecture to generate an optimal realization in hardware implementation by selecting an appropriate scalable factor,i.e.digit size d ,especially in cases involving implementation of ECC cryptosystems in resource-constrained environments.

Scalable multiplication architectures have been developed for PB [11]and NB [10].Correspondingly,this work presents a novel low-complexity scalable architecture for dual basis (DB)multiplication over GF(2m ).The proposed algorithm is derived based on the Hankel matrix-vector representation,from which,a low-complexity scalable and systolic multiplier is then derived.The proposed scalable multiplier is feasible for ?nite ?elds GF(2m )generated by irreducible trinomials.Analytical results indicate that the space complexity of the proposed architecture is signi?cantly lower than that of the conventional digit-serial and bit-parallel multipliers.

II.P reliminaries

As is well known,the ?nite (Galois)?eld GF(2m )can be viewed as a vector space of dimension m over GF(2m ),where the ?eld is generated by irreducible polynomial F (x )=f 0+f 1x +...+f m ?1x m ?1+x m of degree m over GF(2).Assume that αdenotes a root of the irreducible polynomial F (x ).Then,any element A in the ?nite ?eld GF(2m )can be represented as A =a 0+a 1α+a 2α2+···+a m ?1αm ?1,where the coordinates a i ∈GF(2)for 0≤i ≤m ?1.The set {1,α,α2,...,αm ?1}is called the polynomial basis (PB)of GF(2m ).

De?nition 1:The trace function Tr(x )over GF(2m )is de-?ned as [5]Tr(x )= m ?1i =0x 2i

.

De?nition 2:A basis {β0,β1,...,βm ?1}in GF(2m

)is said to be the dual basis (DB)of {1,α,α2,...,αm ?1}if the following condition is satis?ed:

Tr(γαi

βj )=

1,i f i =j ,0,i f i j ,(1)where γis selected to simplify the conversion between poly-nomial and dual bases.

For any two elements A and B in GF(2m

)represented in polynomial and dual basis respectively,i.e.

A =a 0+a 1α+a 2α2+···+a m ?1αm ?1,(2)

B =b 0β0+b 1β1+···+b m ?1βm ?1,

(3)

their product C =AB represented in dual basis,i.e.

C =c 0β0+c 1β1+···+c m ?1βm ?1,

(4)can be computed with the following discrete-time Wiener-Hopf equation (DTWHE)[12]:

?????????????????c 0c 1...c m ?1?????????????????=?????????????????b 0b 1···b m ?1b 1b 2···b m ............b m ?1b m ···b 2m ?2??????????????????????????????????

a 0a 1...a m ?1

?

????????????????(5)where b m +i =f 0b i +f 1b i +1+···+f m ?1b i +m ?1,for i =0,1,···,m ?1.If we de?ne the following vectors:A =[a 0,a 1,···,a m ?1],F =[f 0,f 1,···,f m ?1]and B (i )=[b i ,b i +1,···,b i +m ?1],for i =0,1,···,m ?1,then,b m +i and c i can also be expressed as

b m +i =B (i ) F (6)

c i =B (i ) A

(7)

where “ ”denotes the inner product operation of two vectors.Notably,B (0)=B =[b 0,b 1,···,b m ?1].

Based on (6)and (7),Lee et al.[6]developed a bit-parallel algorithm and corresponding systolic DB multiplier architec-ture consisting of m 2cell,which comprises one AND gate,one XOR gate and two 1-bit latches.Owing to the regularity of its architecture,this DB multiplier is feasible for VLSI implementation.However,for a large ?eld size of binary ?nite ?elds,e.g.the ?ve GF(2m ),m =163,233,283,409and 571,used in ECDSA,the corresponding large space complexity O (m 2)makes such a multiplier infeasible for implementing in constrained hardware environments such as smart cards and mobile handsets.To overcome this problem,the next section introduces a novel scalable scheme for DB multiplication that divides the m -bit operand word into several d -bit digits and,then,iteratively applies a smaller scale multiplier to achieve the complete m -bit multiplication.

III.P roposed S calable D ual B asis M ultiplier over GF(2m )Deriving the scalable architecture of DB multiplier initially requires introducing the Hankel matrix-vector representation.A.Hankel Matrix-Vector Representation

De?nition 3:An m ×n matrix H is referred to as a Hankel matrix if it satis?es the relation H (p ,q )=H (p +1,q ?1),for 0≤p ≤m ?2,1≤q ≤n ?1,where H (p ,q )represents the element in the intersection of row i and column j . A Hankel matrix can be determined entirely by the m +n ?1entries that are located on its ?rst row and last https://www.sodocs.net/doc/4e3733535.html,ly,the matrix can be de?ned by the corresponding Hankel vector H =[h 0,h 1,···,h m +n ?2].With the Hankel matrix-vector representation,the product of a Hankel matrix H and a vector V =[v 0,v 1,···v n ?1],i.e.H V T where T denotes transpose operator,is denoted as ?V .With such notation,the DB multiplication in (5)can be expressed as

C T =B ?A ,

(8)

where B =[b 0,b 1,···,b m ?1,b m ,···,b 2m ?2]represents the corresponding Hankel vector of the Hankel matrix in (5).B.Proposed Algorithm

For A ,B and C de?ned in (2),(3)and (4),repectively,select the digit size as d ,and de?ne k = m /d .If the word length m is divisible by d ,then m =kd .Otherwise,(k ?1)d

to(6).In the resulting C,bits c m,···,c m ?1are redundant and should be disregarded.Thus,in the following,we only consider the case where m is divisible by d.

For the element A expressed in(2),we can rewrite it as

A=A0+A1αd+A2α2d+···+A k?1α(k?1)d(9) where A i=a id+a id+1α+···+a id+d?1αd?1,i=0,1,···,k?1. Then,C can be expressed as

C=BA=B(A0+A1αd+···+A k?1α(k?1)d)

=BA0+BA1αd+···+BA k?1α(k?1)d

=E0+E1αd+···+E k?1α(k?1)d

=((···(E k?1αd+E k?2)αd+···+E1)αd+E0,

(10)

where E i denotes the dual base element BA i,for i= 0,1,···,k?1,i.e.

E i BA i=e i,0β0+e i,1β1+···+e i,m?1βm?1.(11) The j-th coordinate of E i,e i,j,can be obtained,based on De?nition2,as

e i,j=Tr(γαj E i)=Tr(γαj BA i)

=Tr(γαj B(a id+a id+1α+···+a id+d?1αd?1))

=a id Tr(γαj B)+···+a id+d?1Tr(γαj+d?1B)

=a id b j+a id+1b j+1+···+a id+d?1b j+d?1,

(12)

for j=0,1,···,m?1.Expressing(12)in matrix form,we thus get corresponding vector E T i [e i,0,e i,1,···,e i,m?1]T=B A T i, where

A i=[a id,a id+1,···,a id+d?1],(13) for i=0,1,···,k?1,and

B=?

???

???

???

???

???

?

b0b1b2···b d?1

b1b2b3···b d

..

.

..

.

..

.

.....

.

b m?1b m b m+1···b m+d?2

?

???

???

???

???

???

?

.(14)

The matrix expression corresponding to(10)is thus obtained as

C T=[c0,c1,···,c m?1]T

=B A T0+(B A T1)αd+···+(B A T k?1)α(k?1)d

=E T0+E T1αd+···+E T k?1α(k?1)d

=((···(E T k?1αd+E T k?2)αd+···+E T1)αd+E T0.

(15)

The matrix B(eq.(14))in the above equation is a m×d Hankel matrix whose corresponding Hankel vector is

B=[b0,b1,···,b d?1,b d,···,b m?1,b m,···,b m+d?2].(16) With the Hankel matrix-vector representation,eq.(15)can be rewritten as

C T=B?A0+(B?A1)αd+···+(B?A k?1)α(k?1)d

=((···(B?A k?1αd+B?A k?2)αd+

···+B?A1)αd+B?A0 =((···(E T k?1αd+E T k?2)αd+···+E T1)αd+E T0(17)

where E T i=B A T i=B?A i,for i=0,1,···,k?1.Notably,

all contents in all parentheses in(17)are dual basis element

vectors.The whole computation thus involves k Hankel multi-

plications(B?A i,i=0,1,···,k?1)and k nested multiplications

ofαd to dual basis element vectors.

Next,we will derive the e?ect of multiplying byαd for a

dual basis element vector.Suppose that there is a dual basis

element vector E [e0,e1,···,e m?1]whose corresponding

dual basis element is E e0β0+e1β1+···+e m?1βm?1.Now,

multiplying vector E byαd,i.e.Eαd,implies multiplying

element E byαd,i.e.Eαd=(e0β0+e1β1+···+e m?1βm?1)αd.

The j-th coordinate of Eαd can thus be obtained,based on

De?nition2,as

(Eαd)j=Tr(γαj(Eαd))=Tr(γαd+j E)=e d+j,

for j=0,1,···,m?1.Thus,we get the vector Eαd as

Eαd=[e d,e d+1,···,e m?1,e m,···,e d+m?1].(18) From(18),it is clear that the e?ect of multiplying vector

E byαd is just a d-bit left-shifting operation on vector

E.The latter part of coordinates,i.e.the d shifted-in bits,

e m,e m+1,···,e m+d?1,are de?ned as e m+i Tr(γαm+i E),i=

0,1,···,d?1.When the generating function of GF(2m)is

an irreducible trinomial,i.e.F(x)=x m+x n+1,these bits

can be computed as follows:Letαbe the root of F(x),then

αm=αn+1which leads to

e m+i=Tr(γαm+i E)=Tr

γ(αn+1)αi E

=Tr(γαn+i E)+Tr(γαi E)=e n+i+e i,(19) for i=0,1,···,d?1.If n and d are selected to satisfy the

condition0

As a result,from(19),the lattermost d bits of Eαd can be

reformed as

[e m,e m+1,···,e m+d?1]

=[(e n+e0),(e n+1+e1),···,(e n+d?1+e d?1)].

Namely,these d bits can be generated from the coordinate

bits of the original vector E,i.e.e0,e1,···,e m?1,with d XOR

gates since the addition of two bits in GF(2)can be performed

by a XOR gate.The whole Eαd vector can thus be expressed

as

Eαd=[e d,e d+1,···,e m?1,(e n+e0),(e n+1+e1),

···,(e n+d?1+e d?1)](20)

Next,we divide B?A i=B A T i into k parts in order to

adopt a smaller size of DB multiplier architecture.From(13)

and(14),we can rewrite B?A i=B A T i as follows:

B?A i=B A T i

=

?

???

???

???

???

???

?

B0

B1

..

.

B k?1

?

???

???

???

???

???

?

A T i=

?

???

???

???

???

???

?

B0A T i

B1A T i

..

.

B k?1A T i

?

???

???

???

???

???

?

=

?

???

???

???

???

???

???

B0?A i

B1?A i

..

.

B k?1?A i

?

???

???

???

???

???

???

,(21)

where

B j =?????????????????b jd b jd +1b jd +2

···

b jd +d ?1b jd +1b jd +2b jd +3···b jd +d ......

.........b jd +d ?1

b jd +d

b jd +d +1

···

b jd +2d ?2

?

????????????????,(22)

for j =0,1,···,k ?1,are d ×d Hankel matrices whose corresponding 1×(2d ?1)Hankel vectors are B j =[b jd ,b jd +1,···,b jd +d ?1,b jd +d ,···,b jd +2d ?2],

(23)

for j =0,1,···,k ?1.From (21),it reveals that each Hankel multiplication,B ?A i ,can be composed of k smaller size of Hankel multiplications,i.e.B j ?A i ,j =0,1,···,k ?1.For convenience,let b j denote the d -bit length sub-vectors:

b j [b jd ,b jd +1,···,b jd +d ?1],

(24)

for j =0,1,···,k .Then,the (2d ?1)-bit length Hankel vectors B j (eq.(23))can be further expressed as:

j =

b j ,b j +1\b jd +2d ?1 ,(25)for j =0,1,···,k ?1,where b j +1\b jd +2d ?1denotes removing

the lattermost bit b jd +2d ?1from b j +1.Beside,the original Hankel vector B (eq.(16))can be composed of k +1sub-vectors as follows:

B =

b 0,b 1,···,b k ?1,b k .(26)Notably,all b 0,b 1,···,b k ?1can be obtained directly from

the coordinate bits of the original input vector B ,i.e.b 0,b 1,···,b m ?1.On the other hand,sub-vector b k =[b kd ,b kd +1,···,b kd +d ?1]=[b m ,b m +1,···,b m +d ?1]has to be computed from b 0,b 1,···,b m ?1.When the generating function of GF(2m )is an irreducible trinomial,i.e.F (x )=x m +x n +1,then

b m +i =Tr(γαm +i B )=Tr(γαm αi B )=Tr γ(αn +1)αi B

=Tr(γαn +i B )+Tr(γαi B )=b n +i +b i ,for i =0,1,···,d ?1,where αis the root of F (x ).Thus,b k =[b m ,b m +1,···,b m +d ?1]

=[(b n +b 0),(b n +1+b 1),···,(b n +d ?1+b d ?1)].

(27)

Under the condition that n and d are selected as 0

Based on the above derivations,a MSD (most signi?cant digit)?rst scalable dual-basis multiplication algorithm with digit size d is derived as follows:Algorithm 1:

Input :A =[a 0,a 1,···,a m ?1],B =[b 0,b 1,···,b m ?1]Output :C =[c 0,c 1,···,c m ?1]=AB 1.Initial step:

1.1Clear output vector C

1.2Construct vectors A i ,i =0,1,···,k ?1,from A

according to (13)

1.3Construct vectors b j ,j =0,1,···,k ,from B

according to (24)and (27)2.Multiplication step:2.1For i =1to k do

2.2Clear vector E =[e 0,e 1,···,e m ?1]=[E 0,E 1,···,

E k ?1]where E 0,···,E k ?1are d -bit sub-vectors.2.3For j =0to k ?1do 2.4B j = b j ,b j +1\b jd +2d ?1

2.5E j =

B j ?A k ?i T 2.6Endfor 2.7Get E =[E 0,E 1,···,E k ?1]= B 0?A k ?i T ,

B 1?A k ?i T ,···,

B k ?1?A k ?i T = B ?A k ?i T 2.8

C :=C αd according to (20)2.9C :=C +E =C +

B ?A k ?i T 2.10Endfor 3.Return

C .Algorithm 1implements (17)in MS

D ?rst scheme (for PB element A ).The PB element A is divided into k sub-vectors (digits)A i ,i =0,1,···,k ?1.The DB element B is divided into k sub-vectors b j ,j =0,1,···,k ?1,and b k is generated.The complete product result vector C is obtained after all k rounds of computations (outer loop)are performed.In each computation round,k smaller size of Hankel multiplications (j ?A k ?i )are performed (inner loop)to construct the required bigger size of Hankel multiplication (?A k ?i ).Note that the k sub-vectors A i are fed into the computation process in MSD ?rst manner (from A k ?1to A 0).C.Proposed Architecture

Based on Algorithm 1,the proposed MSD scalable architec-ture for dual-basis multiplication over GF(2m )is constructed as shown in Fig.1where the d ×d systolic Hankel multiplier is applied to perform the Hankel matrix-vector multiplications B j ?A k ?i ,and is composed of d 2U-cell as shown in Fig.2.To perform the Hankel multiplication B j ?A k ?i ,the sub-vector A k ?i (eq.(13))is sent into the Hankel multiplier (Fig.2)through the d bits [a 0,a 1,···,a d ?1]on the upper side.The Hankel vector B j (eq.(23))is sent into the multiplier through 2d ?1bits [b 0,b 1,···,b d ?1,b d ,···,b 2d ?2]on the upper and right sides.The d -bit product outcome B j ?A k ?i is then obtained from the d bits [c 0,c 1,···,c d ?1]on the right side of the multiplier.

Back to Fig.1,register A consists of k d -bit latches (A 0,A 1,···,A k ?1)and register B consists of k +1d -bit latches (b 0,b 1,···,b k ?1,b k ).They all function as circular-shift registers.Register E also comprises k d -bit latches which are used to store the outputs of the d ×d systolic Hankel multiplier,i.e.B 0?A k ?i ,B 1?A k ?i ,···,B k ?1?A k ?i .The αd block consists of d XOR gates and is applied to perform the transformation for a dual basis element vector (eq.(20)).Register C is then responsible for accumulating and outputting the result vector C .The frequency of the clock signal CLK1for registers B and E is set to be k times that of the clock signal CLK2for registers A and C,thus k CLK1cycles occur during one CLK2

B B

Fig.1.

Proposed MSD scalable DB multiplier over GF(2m )

456c 0

c 1c 2c 3

Fig.2.d ×d Hankel multiplier applied to perform B j ?A k ?i for d =4

cycle.As a result,the k Hankel multiplication results,i.e.B 0?A k ?i ,B 1?A k ?i ,···,B k ?1?A k ?i ,are sequentially outputted from the Hankel multiplier and stored into register E during one CLK2cycle (step 2.3–2.7).When the

next CLK2cycle starts,register C receives the sum of the αd transformation of its previous content and the content of register E (step 2.8–2.9).After k computation rounds,the desired result vector C T =B ?A 0+(B ?A 1)αd +···+(B ?A k ?1)α(k ?1)d (eq.(17))is accumulated in register C.D.Time and space complexity

The proposed MSD scalable DB multiplier architecture contains one d ×d systolic Hankel multiplier (Fig.2)which consists of d 2U-cells.Each U-cell (Fig.3)consists of one AND gate,one XOR gate and two 1-bit latches.The summa-tion circuit (⊕)and the αd block consist of m XOR gates and d XOR gates,respectively.Additionally,registers A,C and E are all composed of k d -bit latches,respectively.Registers B then consists of k +1d -bit latches.Thus,for the proposed MSD

+j

c i

c Fig.3.

Detailed circuit of a U-cell (symbol

?denotes 1-bit latch)

scalable DB multiplier architecture,totally d 2AND gates,d 2+d +kd XOR gates and 4kd +2d 2+d 1-bit latches are required.Table 1lists these gate counts.

As for the computation latency of the proposed scalable multiplier,Algorithm 1clearly indicates that k computation rounds and then k Hankel matrix-vector computations in each round are required.Hence,totally k 2Hankel matrix-vector computations are required to perform a complete m -bit multi-plication.Each Hankel matrix-vector computation performed with the d ×d systolic Hankel multiplier (Fig.2)requires a latency of 2d ?1clock cycles (CLK1)[6].Moreover,due to the feedback structure of the summation circuit for register C,the ?nal resultant vector C is obtained after k computation rounds.Each computation round involves k clock cycles to let register E be ?lled with ?A k ?i (i.e.,0?A k ?i ,1?A k ?i ,···,B k ?1?A k ?i )and then send this content forward to register C.Thus,the total latency required to obtain the desired complete result of vector C is k 2+2d ?2clock cycles.Additionally,critical path delay is the time duration required by each U-cell in the d ×d systolic Hankel multiplier.This time duration is T A +T X +T L where T A ,T X and T L refer to the time delay of a 2-input AND gate,a 2-input XOR gate and an 1-bit latch,respectively.Table 1summarizes the above space complexity (gate count)and time complexity (latency and critical path delay)of the proposed scalable multiplier.This table also compares the proposed multiplier architecture with other non-scalable multipliers (bit-parallel [6]and digit-serial [8],[9]).According to this table,the proposed scalable multiplier ar-chitecture has a lower space complexity in terms of total gate count (O (d 2))than the non-scalable architectures (O (m 2)and O (kd 2)for bit-parallel and digit-serial ones,respectively).It clearly demonstrates the superiority of the proposed scalable multiplier architecture.

IV .C onclusions

This work develops a novel low-complexity scalable ar-chitecture for dual basis multiplications over GF(2m ).The proposed multiplier architecture is derived from the Hankel matrix-vector representation of dual basis multiplication,and is feasible for GF(2m )generated by irreducible trinomials.Analytical results exhibit that the space complexity of the pro-posed scalable architecture is substantially lower than that of the non-scalable architectures.Besides,the proposed scalable architecture can achieve,by appropriately selecting its digit

TABLE I

C omparisons between various multipliers over GF(2m)

Multiplier Kim et al.

[9]Ibrahim et

al.[8]

Lee et al.[6]Proposed

(Fig.1)

Basis Polynomial Dual Dual Dual Architecture Digit-serial Digit-serial Bit-parallel Scalable Space complexity:

#2-input AND k(2d2+d)2kd2m2d2

#2-input XOR2kd22kd2m2d2+d+kd #1-bit latch10kd+k6kd2m2+m4kd+2d2+d #1×2SW00m0

#2×1MUX2kd d m0

Critical path delay time dT A+

dT X+(d?

1)T MUX+T L

T A+2dT X+

T MUX+T L

T A+T X+T L T A+T X+T L

Latency(unit=

cycle)

3k2k2m k2+2d?2

k= m/d ,d:selected digit size

size,a satisfactory trade-o?between hardware complexity and throughput performance for implementing ECC cryptosystems such as ECDSA in resource-constrained environments such as embedded systems.Moreover,due to its regularity,modularity and concurrency,the proposed scalable multiplier architecture is highly promising for VLSI implementations.

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扫描二维码 unlock the smart lock 解开智能锁 timer 计时器 user 用户 smartphone 智能手机 keep fit 健身 environmental protection/ environment friendly/ help the environment 环保的 In full swing 如火如荼 brightly coloured 色彩鲜艳 The combination of technology, creativity and market forces 科技、创意、市场力量的结合 has changed the image of the city 改变了城市形象

curb carbon dioxide emissions 减少二氧化碳排放 reduce road congestion 减少道路拥堵的情况 random parking 随机停车 illegal parking 乱停乱放 bicycle damage 车辆损坏 traffic violation 违章 social mind 公德心 quality 素质 范文篇 (一) 假定你是红星中学初三学生李华。你的美国朋友Jim在给你的邮件中提到他对中国新近出现的一种共享单车“mobike”很感兴趣，并请你做个简要介绍。请你给Jim回信，内容包括： 1. 这种单车的使用方法(如：APP查看车辆、扫码开锁等);

暑假去北京的英语作文

暑假去北京的英语作文 北京是我国的首都，有许多历史文化建筑，那么关于暑假去北京的英语作文怎么写呢?以下是为大家整理的暑假去北京游玩的英语作文，欢迎大家阅读。 暑假去北京游玩的英语作文篇一This summer holiday I visited to Beijing with my aunt. We visited to many famous places such as Tian'ann Men Square the Imperial Palace the Summer Palace the Great Wall and so on. Before that I just saw them on TV but this summer holiday they were all in front of my eyes. I was so exciting. Among them I like theSummerPalacethe most because it's so amazing and the scenery is very beautiful. BesidesBeijingis a modern city. There are many tall buildings. I like this city very much and I hope I can visit there again. 翻译： 这个暑假，我和叔叔到北京旅游。我们参观了很多地方，比如天安门广场，故宫，颐和园和长城等等。 在那之前我只是在电视上看见过它们，但是这个暑假我亲眼看到它们就在我的前面，我很兴奋。

ARoseforEmily英文分析及简评

is divided into five secti ons. A Rose for Emily The first sect ion ope ns with a descripti on of the Griers on house in Jeffers on. The n arrator men ti ons that over the past 100 years, Miss Emily Griers on ' s home has fall into disrepair and become “ an eyesore among eyesores. ” The first sentence of the story sets the tone of how the citize ns of Jeffers on felt about Emily: “ When Miss Emily Griers on died, our whole town went to the funeral: the men through a sort of respectful affection for a fallen monument, the wome n mostly out of curiosity to see the in side of her house, which no one save an old man serva nt -a comb ined garde ner and cook - had see n in at least ten years. It is known around tow n that Emily Griers on has not had guests in her home for the past decade, except her black serva nt who runs errands for her to and from the market. When a new city council takes over, however, they begi n to tax her once aga in. She refuses to pay the taxes and appear before the sheriff, so the city authorities invite themselves into her house. When confron ted on her tax evasi on, Emily reminds them that she does n't have to pay taxes in Jeffers on and to speak to Colonel Sartoris, although he had died 10 years before. In section two, the narrator explains that the Griersons had always been a very proud Souther n family. Mr. Griers on, Emily ' s father, believes no man is suitable for his daughter and does n't allow her to date. Emily is largely depe nden t upon her father, and is left foun deri ng whe n he dies. After Mr. Griers on's death, Emily does not allow the authorities to remove his body for three days, claiming he is still alive. She breaks down and allows authorities to take the body away for a quick burial. Section three introduces Emily ' s beau, Homer Barron, a foreman fronthe north. Homer comes to Jeffers on with a crew of men to build sidewalks outside the Griers on home. After Emily and Homer are seen driving through town several times, Emily visits a druggist. There, she asks to purchase arse nic. The druggist asks what the arse nic is for since it was required of him to ask by law. Emily does not respond and coldly stares him down un til he looks away and gives her the arse nic. When Emily ope ns the package, underneath the skull and bones sign is written, "For Rats." Citize ns of Jeffers on believe that Miss Emily is going to commit suicide si nce Homer has not yet proposed in the beg inning of sect ion four. The tow nspeople con tact and in vite Emily's two cousins to comfort her. Shortly after their arrival, Homer leaves and then retur ns after the cous ins leave Jeffers on. After stay ing in Jeffers on for one ni ght, Homer is never seen again. After Homer ' s disappearance, Emily begins to age, gain weight, and is rarely see n outside of her home. Soon, Miss Emily passes away.