Fast transient response CFA-based LDO regulator

Fast Transient Response CFA-Based LDO Regulator

Alireza Saberkari Microelectronics Research Lab., Dept. of Electrical

Engineering

University of Guilan

Rasht, Iran

Email: a_saberkari@guilan.ac.ir

Herminio Martinez and Eduard Alarcón

Dept. of Electronic Engineering

Technical University of Catalunya

Barcelona, Spain

Email: {herminio.martinez, eduard.alarcon}@https://www.sodocs.net/doc/3d15732378.html,

Abstract—In this paper a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) is presented. The utilized CFA consists of an open-loop voltage follower with output local current-current feedback based on a level-shifted flipped voltage follower (LSFVF) to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. The circuit does not require any internal compensation capacitor and is stable for a wide range of output load currents 0-100 mA and a 1μF output capacitor. Post-layout simulation results for a 0.35μm CMOS process reveal that the maximum output voltage deviation of the proposed LDO for 0-100mA load transient with rise and fall times of 10 and 100ns is only 3mV, and the PSRR is smaller than -56dB over the entire load current range.

I.I NTRODUCTION

Portable electronic devices like cellular phones and PDAs need efficient energy management in order to reduce the standby power consumption and increase the battery life whereas high speed microprocessors require stable supply voltages whilst demanding fast varying load currents. Low-dropout regulators (LDOs) are widely used alone in many integrated power management circuits but also used as post regulators of switching converters, as they can provide wideband regulated low noise supply voltage for noise-sensitive analog and RF loads. A typical LDO consists of an error amplifier for detecting the error between the reference and output voltage, a pass transistor controlled by an error amplifier for delivering current to the load, a feedback network, and an output capacitor. There are several performance metrics to be fulfilled when designing an LDO, such as closed-loop stability for a wide range of loads, static regulation in front of input voltage and load variations, and fast rejection of steep transient load variations [1, 2]. Different techniques have hitherto been proposed for stability, such as the pole-zero cancellation method in [2] and pole-splitting schemes in [3-5]. In [6], an internal zero generated through a voltage-controlled current source (VCCS) is used for frequency response compensation and enhanced stability. Dual-loop feedback in the form of using a current buffer approach in the compensation network is another way to

improve transient response and stability, which was proposed

Figure 1. Proposed LDO architecture based on CFA

in [7-10]. LDOs based on the flipped voltage follower (FVF) were introduced in [11, 12]. In [11], the FVF was applied to the design of a power stage, and in [12], the LDO operated in an open-loop configuration. Recently, current-mode LDOs have been proposed in which the pass transistor operates like a voltage-controlled current source [13, 14]. With this method, the LDO dropout is minimized and high power supply ripple rejection (PSRR) can be achieved. In [15], an LDO with a current feedback amplifier (CFA) is proposed as a buffer in order to enhance the transient response of the regulator.

In previously reported LDOs, voltage-mode operational amplifiers are used as error amplifiers, thereby limiting the regulator performance due to their fixed gain-bandwidth product and limited slew rate. Complementarily, a strategic design target is to avoid on-chip compensating capacitors, which occupy a large chip area thus achieving the required stability using only external off-chip load capacitance [3]. In face of the above considerations, in this paper a CMOS current-steering LDO regulator based on a CFA exhibiting fast transient stable performance is presented.

II.P ROPOSED LDO A RCHITECTURE

Fig. 1 shows the block diagram of the proposed LDO. The control mechanism of the pass transistor in the LDO is carried out by a CFA which is based on the conjunction of an open-loop voltage follower with current-copying capability

Figure 2. Schematic of the proposed LDO

and an inverting output buffer. The output signal is transferred

to the inverting input of the CFA (X node, which has very low impedance), through the feedback network, and is compared

to the reference voltage. This comparison result is amplified through the transimpedance gain of the CFA thereby

controlling the gate of the pass transistor. Very low impedance

at the inverting input of the CFA is the key to achieve high regulation and fast transient response.

The transistor-level schematic of the proposed LDO is shown in Fig. 2. The circuit is composed of a CFA consisting of a class AB voltage follower, M 1-M 12, plus an inverting output buffer, M 13, M 14, a pass transistor M P , and a feedback network R 1 and R 2. In order to achieve high input impedance, the reference voltage V ref is fed to the circuit

through a simple unity-gain amplifier, which is not shown in Fig. 2. Since the bias conditions and sizes of transistor pairs (M 1-M 3) and (M 2-M 4) are equal, it is inferred that V 1SG =V 3SG , V 2GS =V 4GS and hence the generated reference

voltage through the unity-gain amplifier appears at the output

node.

III. S TABILITY C ONSIDERATIONS In order to consider the stability of the LDO, first of all the frequency response of the input voltage follower based on

LSFVF with local current-current feedback should be evaluated. The simplified schematic of the LSFVF is shown in

Fig. 3(a). Transistor M 2 provides shunt feedback and

transistor M 3 is a level shifter to increase the swing of the buffer. Loop-gain analysis is done by breaking the local feedback loop at the gate of M 3 and applying a test signal, as shown in Fig. 3(b). The circuit has three open-loop poles

at OLi i Pi R C 1=ω, where i C and OLi R are the parasitic capacitance and open-loop resistance at node i . The open-loop resistances at different nodes of the circuit are as follows:

Figure 3. (a) Simplified schematic of LSFVF (b) equivalent circuit for

open-loop analysis

2111||o o m b OL r r g r R ≈ 2112||1(1o o b m OL r r r g R +≈

(1) b m OL r g R ||133≈

where b r is the output resistance of current source b I .

For 1o b r r ≈, the open-loop resistances tend to 11o OL r R ≈, 122m OL g R ≈, and 331m OL g R ≈. The circuit has an open-loop gain of 1212o m OL m OL r g R g A ?≈?= and its gain-bandwidth product is equal to 12C g GBW m =. As it can be seen, LSFVF has a dominant pole at node 1 and two high

frequency poles at nodes 2 and 3. The condition GBW P P 2&32>ωω ensures stability of the circuit which is easily achieved by proper sizing of transistors M 1- M 3

.

On the other hand, closed-loop poles at different nodes of

the LSFVF are needed to evaluate the AC response of the

overall LDO. These are located at CLi i PCLi R 1=ω, in which

CLi R is the closed-loop resistance at node i . CLi R for

different nodes of LSFVF is given by: 21111m OL OL CL g A R R ≈+=

121222

1o m m OL

OL CL r g g A R R ≈+= (2)

132331

1o m m OL

OL CL r g g A R R ≈+=

Figure 4. Equivalent small signal model of the proposed LDO

As it is obvious from Eq. (2), output resistance of the LSFVF (2CL R ) is much lower than the conventional buffer which helps to achieve high regulation and fast transient response. Also, the dominant closed-loop pole of the LSFVF is located at a high frequency of 121111C g R m CL PCL ≈=ω and the two other poles are at much higher frequencies than 1PCL ω. So the effect of poles and output resistance of the LSFVF can be neglected for the overall LDO stability analysis. The equivalent small signal model of the proposed LDO is

shown in Fig. 4 in which the LSFVF is modeled by an ideal

unity-gain buffer and a very small output resistance R buffer as

mentioned before, and the unity-gain current-controlled current source represents the current-copying capability of the input buffer of LDO. Breaking the feedback loop, inserting a test signal, V TI , and receiving the output signal, V TO , yields the loop-gain of the LDO which is given by:

)

1)(1)(1()1(3

2

1

1

p p p z loop TI

TO s

s

s

s

A V V

ωωωω+

+

+

+?≈

(3)

where

))((212

dsp mp buffer

a loop r g R R R R R A =

dsp out p r C 11≈ω , a

a p R C 1

2=ω (4)

b b p R C 13=

ω , esr

out z R C 1

1=ω In Eq. (4),1211||ds ds a r r R =, 141m b g R =, and esr R is the

equivalent series resistance of the output capacitor, out C . The dominant pole of the LDO is 1p ω. The second pole 2p ωis designed to cancel out with the left half-plane (LHP) zero 1z ω. The third pole 3p ω is located at a higher frequency than the unity-gain frequency. Hence, the proposed LDO operates as a single pole system and is stable with a 1 μF output capacitor.

IV. P OST -LAYOUT C HARACTERISATION

The proposed LDO topology has been designed and laid out, and the obtained results in this section correspond to HSPICE post-layout simulations in a 0.35μm CMOS process. The LDO does not require any compensation capacitor and is stabilized by an output capacitor in the range of 1μF. The

LDO is designed to source a nominal output current between 0-100mA and consumes a small quiescent current of 59μA under no-load and 189μA under full-load condition, which corresponds to a worst case current efficiency of 99.8%. The measured load and line regulations are 25μV/mA and 13.5mV/V, respectively.

The power supply ripple to output (PSR) of the LDO with a 1μF output capacitor for I load =0 mA and 100 mA is shown

in Fig. 5. The simulated PSR is smaller than -56dB over the entire load current range. The open-loop AC response of the proposed LDO with a 1 μF output capacitor is shown in Fig. 6. As it can be seen, the LDO is stable over the entire load current and has a phase margin of 63 and 85 degrees at load currents of 1 and 100 mA, respectively. Load transient responses of the designed LDO with a 1μF output capacitor to the 0-100mA load transient with rise and

fall time of 10 and 100ns is shown in Fig. 7. It is observed that

the LDO can react to fast load current changes and is stable

over the entire load current with a maximum output voltage

deviation of only 3mV.

Figure 5.

PSR of the proposed LDO with 1μF output capacitor

Figure 6.

Open-loop AC response with a 1μF output capacitor

Figure 7. Load transient with a 1 μF output capacitor (a) load transient with 10 ns rise and fall time (b) load transient with 100 ns rise and fall time

TABLE I. P ERFORMANCE SUMMARY AND COMPARISON Parameter [7] [12] [14] [15] This

Work Technology (μm) 0.35

0.35

0.35

0.25

0.35

I Max load ,( mA) 200 50 50 50 100 V in ( V) 2-5.5 1.2-1.5 1.05-3.5 2-2.5 3-5

V out ( V) 1.8 1 0.9 1.5-1.97 2.8

Compensation Cap. (pF) Yes 10 No No Yes No Output Cap. (μF)

1

1

1

0.05

1

I q ( μA) 20-320 95 4.04-164 100 59-189 PSRR (dB)

>45 (0Hz-20KHz) N.A. >50 (0Hz-1MHz) 43 @30 KHz >56

(0Hz-100MHz)

out V Δ( mV)

54 30 6.6 15 3 R T ( μs) 0.27 0.6 0.132 0.03 0.03 FOM (ns)

0.027

1.14

0.0106

0.06

0.0177

Table I provides a performance comparison between the proposed LDO and recently published designs. The figure of merit

(FOM=Max load q R I I T ,×) used in [11] is adopted here to compare

the transient response of different LDOs by evaluating the effect of

the quiescent current I q to the load transient response time (T R ). The T R of the LDO is given by Max load out out R I V C T ,Δ=, where out V Δ is the maximum transient output voltage variation. A lower FOM implies a better transient response achieved by the LDO. By using a 1μF output capacitor in the proposed LDO, the maximum output voltage variation is 3mV and T R is equal to 0.03μs. Hence, as it is observed, the FOM of the proposed LDO is very comparable to that in [14] and smaller than other reported LDOs. By using the quiescent current value at full-load conditions when deriving the FOM, the FOM of the proposed LDO will be notably smaller than that in [14].

V. C ONCLUSION

A current-steering fast transient response LDO based on a CFA is presented. The circuit does not require any internal compensation capacitor and is stable for a wide range of output load currents 0-100

mA and a 1μF output capacitor. Post-layout simulation results for a 0.35μm CMOS process show that the proposed LDO demands 59μA quiescent current at no-load condition and in the worst case has a

current efficiency of 99.8%. With a 1μF output capacitor, the maximum output voltage deviation for a 0-100mA load transient with

rise and fall times of 10 and 100ns is only 3mV and the PSRR is

smaller than -56dB over the entire load current range.

A CKNOWLEDGMENT

Partial funding by projects TEC2007-67988-C02-01, TEC2010-15765, and RUE CSD2009-00046 (Consolider-Ingenio 2010), from the Spanish Ministry of Science and Innovation. R EFERENCES

[1] R.K. Dokania and G.A. Rincon-Mora, “Cancellation of load regulation in low dropout regulators,” Electron Lett., Vol. 38, no. 22, pp. 1300-1302, Oct. 2002.

[2] G.A. Rincon-Mora and P.E. Allen, “Optimized frequency-shaping circuit topologies for LDOs,” IEEE Trans. Circuits Syst. II, Analog Digital Signal Process., vol. 45, no. 6, pp. 703-708, Jun. 1998.

[3] K.L. Leung and P.K.T. Mok, “A capacitor-free CMOS low-dropout

regulator with damping-factor-control frequency compensation,” IEEE J. Solid-State Circuits , vol. 38, no. 10, pp. 1691-1702, Oct. 2003. [4] S.K. Lau, P.K.T. Mok, and K.N. Leung, “A low-dropout regulator for

SoC with Q-reduction,” IEEE J. Solid-State Circuits , vol. 42, no. 3, pp.

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[5] W.J. Hung, S.H. Lu, and S.I. Liu, “CMOS low dropout linear regulator

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[7] M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation,” IEEE J. Solid-State Circuits , vol. 42, no. 8, pp. 1732-1742, Aug. 2007.

[8] G.A. Rincon-Mora, “Active capacitor multiplier in Miller-compensated

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dropout regulators,” Proc. IEEE 32nd Power Electron. Specialists Conf. (PSEC’01), Jun. 2001, pp. 1265-1269. [10] R.J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, “Full on-chip CMOS low-dropout voltage regulator,” IEEE Trans. Circuits Syst.

I , vol. 54, no. 9, pp. 1879-1890, Sept. 2007. [11] P. Hazucha, T. Karnik, B. Bloechel, C. Parsons, D. Finan, and S.

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[12] T.Y. Man, K.L. Leung, C.Y. Leung, P.K.T. Mok, and M. Chan, “Development of single-transistor-control LDO based on flipped voltage follower for SoC,” IEEE Trans. Circuits Syst. I , vol. 55, no. 5, pp. 1392-1401, Jun. 2008.

[13] G. Thiele and E. Bayer, “Current-mode LDO with active dropout

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Case 1 Dear Editor, We would like to submit the enclosed manuscript entitled "GDNF Acutely Modulates Neuronal Excitability and A-type Potassium Channels in Midbrain Dopaminergic Neurons", which we wish to be considered for publication in Nature Neuroscience. GDNF has long been thought to be a potent neurotrophic factor for the survival of midbrain dopaminergic neurons, which are degenerated in Parkinson’s disease. In this paper, we report an unexpected, acute effect of GDNF on A-type potassium channels, leading to a potentiation of neuronal excitability, in the dopaminergic neurons in culture as well as in adult brain slices. Further, we show that GDNF regulates the K+ channels through a mechanism that involves activation of MAP kinase. Thus, this study has revealed, for the first time, an acute modulation of ion channels by GDNF. Our findings challenge the classic view of GDNF as a long-term survival factor for midbrain dopaminergic neurons, and suggest that the normal function of GDNF is to regulate neuronal excitability, and consequently dopamine release. These results may also have implications in the treatment of Parkinson’s disease. Due to a direct competition and conflict of interest, we request that Drs. XXX of Harvard Univ., and YY of Yale Univ. not be considered as reviewers. With thanks for your consideration, I am Sincerely yours, case2 Dear Editor, We would like to submit the enclosed manuscript entitled "Ca2+-binding protein frequenin mediates GDNF-induced potentiation of Ca2+ channels and transmitter release", which we wish to be considered for publication in Neuron. We believe that two aspects of this manuscript will make it interesting to general readers of Neuron. First, we report that GDNF has a long-term regulatory effect on neurotransmitter release at the neuromuscular synapses. This provides the first physiological evidence for a role of this new family of neurotrophic factors in functional synaptic transmission. Second, we show that the GDNF effect is mediated by enhancing the expression of the Ca2+-binding protein frequenin. Further, GDNF and frequenin facilitate synaptic transmission by enhancing Ca2+ channel activity, leading to an enhancement of Ca2+ influx. Thus, this study has identified, for the first time, a molecular target that mediates the long-term, synaptic action of a neurotrophic factor. Our findings may also have general implications in the cell biology of neurotransmitter release. 某杂志给出的标准Sample Cover Letter Case 3 Sample Cover Letter Dear Editor of the : Enclosed is a paper, entitled "Mobile Agents for Network Management." Please accept it as a candidate for publication in the . Below are our responses to your submission requirements. 1. Title and the central theme of the article. Paper title: "Mobile Agents for Network Management." This study reviews the concepts of mobile agents and distributed network management system. It proposes a mobile agent-based implementation framework and creates a prototype system to demonstrate the superior performance of a mobile agent-based network over the conventional client-server architecture in a large network environment.

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FAST迅捷路由器设置教程

FAST迅捷路由器设置教程 各位读友大家好！你有你的木棉，我有我的文章，为了你的木棉，应读我的文章！若为比翼双飞鸟，定是人间有情人！若读此篇优秀文，必成天上比翼鸟！ 篇一：迅捷无线路由器设置教程(图解)迅捷无线路由器设置教程(图解) 文章类型：网络技术原创：天诺时空随着计算机网络应用的不断发展壮大，现有的网络规模早已不能满足其网络规模的扩大化需求，因此扩展互联网应用的能力是一个网络在设计和建设过程中必须要考虑的。如今一台电脑已不再满足需求，如何让更多的终端设备实现共享上网呢？相信有很多的朋友都在关心这个问题，下面开始介绍Fast无线路由器的设置方法。迅捷无线路由器设置（详细设置）一、设备的物理连接有线连接的电脑连接路由器的LAN口，外网过来的网线连接路由器的WAN口，无线连接的通过路由器设置后通过无线功能连

接到路由器。(如下图) 二、建立正确的网络设置 2.1设置电脑的IP地址。右键点击“网上邻居”——“属性”(如下图) “本地连接”——“属性”(如下图) 如下图点击TCP/IP后点击“属性”如下图所示，将IP地址设置为“自动获取IP地址” 2.2测试令检查您的计算机和路由器之间是否连通。点击“开始”——“运行”——“输入CMD”点击确定。在打开的CMD窗口中输入ping 192.168.1.1 其结果显示如下。说明已近与路由器连通了。三、设置路由器打开IE浏览器输入路由器的地址：http://192.168.1.1 ，您将会看到下图所示登录界面。您需要以系统管理员的身份登录，即在该登录界面输入用户名和密码(用户名和密码的出厂设置均为admin)，然后单击确定按钮。如果用户名和密码正确，浏览器将显示管理员模式的画面，并会弹出一个如下图的设置向导页面(如果没有自动弹出的话，可以单击管理员模式画面左边设置向导菜单将它激活)。篇二：

消息导语的写法

消息导语的写法 导语是消息的重要组成部分，是消息的开头，通常是指消息的第一个自然段。消息导语的写作，是新闻记者的基本功。美国大学新闻学院的大学生或研究生要花一年的时间专门学习导语的写作。许多人构思和写作导语的时间要占据通篇稿件的三分之一到一半。由此可见导语写作的难度和重要性。 导语最基本的要求是言简意赅，即用最简洁凝炼的语言将消息中最新鲜、最主要、最精彩、最生动、最吸引人的新闻事实表现出来。导语的写法千变万化、灵活多样。概括起来，大致可以分为下列8种。 一、概要式：即用叙述的方式来归纳概括新闻的要点。 如：新华社1949年4月22日电人民解放军百万大军，从一千余华里的战线上，冲破敌阵，横渡长江。 再如：本报讯中国科学院昆明动物研究所培育计划中的第一只白猴于5月1日降生。（1988年全国好新闻消息二等奖，原载《云南日报》1988 年6月29日一版） 再如：本报讯（记者李捷）613万考生迎来了他们一生一博的时刻-2003年非典时期的正常高考今天静静拉开帷幕。（第十四届中国新闻奖二等奖消息作品） 一、描写式：即用现场目击、白描勾勒的方式来切入。 如：新华社北京1982年7月16日电（记者郭玲春）鲜花、翠柏丛中，安放着中国共产党员金山同志的遗像。千余名群众今天默默走进首都剧场，悼念这位人民的艺术家o（第四届中国新闻奖消息一等奖作品） 再如：本报讯（记者健吾）古埃及的金字塔、法国的巴黎圣母院、缅甸的仰光大金塔、加拿大的尼亚加拉瀑布，还有列宁的墓、白求恩的故居以及日本的劈啪舞……人们不用出国，在五泉山公园文昌宫举行的《劳崇聘外国风光写生展览》上，便可欣赏到外国的名胜古迹，领略到外国的风土人情。（原载《兰州晚报》1985年10月8日四版）再如：本报讯（记者健吾）大西北一个偏僻山村的崎岖小道上，一支娶亲的人马抬着花轿，拥着新郎入场，由此引出一个凄凉的、为人们所熟悉 却又弄不清发生在何年何月的故事。这是省歌剧团为建国40周年正在排练的献礼之作——《阴山下》的序幕o（《兰州晚报》1989年3月5日四版） 三、提问式：即先提出问题，引出悬念，进而解答。

迅捷(FAST)无线路由器设置图解

迅捷(FAST)无线路由器设置图解 下面介绍下Fast FW300R无线路由器宽带共享上网的设置图解。随着网络的发展无线路由器已近逐步的普及到家庭用户中了。本网站主要介绍各类路由器设置的图解教程，下面开始介绍Fast无线路由器的设置方法 一、设备的物理连接 有线连接的电脑连接路由器的LAN口，外网过来的网线连接路由器的WAN口，无线连接的通过路由器设置后通过无线功能连接到路由器。(如下图) 二、建立正确的网络设置 2.1设置电脑的IP地址。右键点击“网上邻居”——“属性”(如下图)

“本地连接”——“属性”(如下图) 如下图点击TCP/IP后点击“属性”

如下图所示，将IP地址设置为“自动获取IP地址”

2.2测试令检查您的计算机和路由器之间是否连通。点击“开始”——“运行”——“输入CMD”点击确定。在打开的CMD窗口中输入ping 192.168.1.1 其结果显示如下。说明已近与路由器连通了。 三、设置路由器 打开IE浏览器输入路由器的地址：http://192.168.1.1 ，您将会看到下图所示登录界面。您需要以系统管理员的身份登录，即在该登录界面输入用户名和密码(用户名和密码的出厂设置均为admin)，然后单击确定按钮。

如果用户名和密码正确，浏览器将显示管理员模式的画面，并会弹出一个如下图的设置向导页面(如果没有自动弹出的话，可以单击管理员模式画面左边设置向导菜单将它激活)。

▲登录路由器后的主画面可以手动点击设置向导进行设置 单击下一步，进入上网方式选择画面。这里我们演示一般家庭用户所采用的PPPOE拨号上网的方式。具体根据您的实际情况。 在如下图的界面中输入ISP提供的宽带上网的用户名和密码。