单片机基础外文翻译参考文献

单片机基础外文翻译参考文献

(文档含中英文对照即英文原文和中文翻译)

原文:

Fundamentals of Single-chip Microcomputer

Dr. Dobbs MacintoshJournal

Abstract

T h e s i n gl e-chi p m i c r o com pu t er i s t h e cul m i na t i on of bo t h t h e d e v el opm e nt o f t h e di gi t al c om p ut e r a nd t h e i nt e gra t e d c i r c ui t a rgu a b l y t h e t ow m o s t s i gn i fi c ant i nv en t i on s of t h e 20t h ce n t u r y .

T h es e t o w t yp e s o f a rc hi t e c t u r e a r e fo un d i n s i n gl e-c hi p

m i c r o com pu t e r.S om e e m p l o y t h e s pl i t p ro gr a m/d at a m em o r y o f t h e H a r v a rd a r ch i t e ct u r e, s ho wn i n F i g.3-5A-1, ot h er s f o l l o w t he p hi l o so ph y,w i d e l y a d a p t ed f o r ge n e r al-pu rp os e com p ut e rs and m i c r op r oc e s s o rs,of m ak i n g n o l o gi c al di s t i nc t i on be t w ee n p ro gr a m a n d d at a m em o r y a s i n t h e P r i n c et on ar c hi t e ct u r e.

In ge n e r a l t er m s a si n gl e-c hi p m i cro c om put e r i s c ha r ac t e ri z ed b y t h e i n co r po r at i o n o f al l t h e u ni t s o f a c om put e r i n t o a s i n gl e d e vi c e.

Keyword: Single-chip Microcomputer ROM RAM Programming Algorithm Features

? Compatible with MCS-51? Products

? 4K Bytes of In-System Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

? Fully Static Operation: 0 Hz to 24 MHz

? Three-level Program Memory Lock

? 128 x 8-bit Internal RAM

? 32 Programmable I/O Lines

? Two 16-bit Timer/Counters

? Six Interrupt Sources

? Programmable Serial Channel

? Low-power Idle and Power-down Modes

Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard MCS-51 instruction set and pinout. The

on-chipFlash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded control

applications.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset.

Pin Configurations

Block Diagram

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.

Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external programand data memory. In this mode P0 has internalpullups.

Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during program verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order

address bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:

Port 3 also receives some control signals for Flash programming

and verification.

ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external program memory.When the

AT89C51 is executing code from external programmemory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program

execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

Figure 1. Oscillator Connections

Figure 2. External Clock Drive Configuration

Power-down Mode

In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

Program Memory Lock Bits

On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the

AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.

The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.

Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.

1. Input the desired memory location on the address lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V for the high-voltage programming mode.

5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms.Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.

Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can also be monitored by the

土木工程外文翻译.doc

项目成本控制 一、引言 项目是企业形象的窗口和效益的源泉。随着市场竞争日趋激烈，工程质量、文明施工要求不断提高，材料价格波动起伏，以及其他种种不确定因素的影响，使得项目运作处于较为严峻的环境之中。由此可见项目的成本控制是贯穿在工程建设自招投标阶段直到竣工验收的全过程，它是企业全面成本管理的重要环节，必须在组织和控制措施上给于高度的重视，以期达到提高企业经济效益的目的。 二、概述 工程施工项目成本控制，指在项目成本在成本发生和形成过程中，对生产经营所消耗的人力资源、物资资源和费用开支，进行指导、监督、调节和限制，及时预防、发现和纠正偏差从而把各项费用控制在计划成本的预定目标之内，以达到保证企业生产经营效益的目的。 三、施工企业成本控制原则 施工企业的成本控制是以施工项目成本控制为中心，施工项目成本控制原则是企业成本管理的基础和核心，施工企业项目经理部在对项目施工过程进行成本控制时，必须遵循以下基本原则。 3.1 成本最低化原则。施工项目成本控制的根本目的，在于通过成本管理的各种手段，促进不断降低施工项目成本，以达到可能实现最低的目标成本的要求。在实行成本最低化原则时，应注意降低成本的可能性和合理的成本最低化。一方面挖掘各种降低成本的能力，使可能性变为现实；另一方面要从实际出发，制定通过主观努力可能达到合理的最低成本水平。 3.2 全面成本控制原则。全面成本管理是全企业、全员和全过程的管理，亦称“三全”管理。项目成本的全员控制有一个系统的实质性内容，包括各部门、各单位的责任网络和班组经济核算等等，应防止成本控制人人有责，人人不管。项目成本的全过程控制要求成本控制工作要随着项目施工进展的各个阶段连续 进行，既不能疏漏，又不能时紧时松，应使施工项目成本自始至终置于有效的控制之下。 3.3 动态控制原则。施工项目是一次性的，成本控制应强调项目的中间控制，即动态控制。因为施工准备阶段的成本控制只是根据施工组织设计的具体内容确

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专业资料 学院： 专业：土木工程 姓名： 学号： 外文出处：Structural Systems to resist (用外文写) Lateral loads 附件：1.外文资料翻译译文；2.外文原文。

附件1：外文资料翻译译文 抗侧向荷载的结构体系 常用的结构体系 若已测出荷载量达数千万磅重，那么在高层建筑设计中就没有多少可以进行极其复杂的构思余地了。确实，较好的高层建筑普遍具有构思简单、表现明晰的特点。 这并不是说没有进行宏观构思的余地。实际上，正是因为有了这种宏观的构思，新奇的高层建筑体系才得以发展，可能更重要的是：几年以前才出现的一些新概念在今天的技术中已经变得平常了。 如果忽略一些与建筑材料密切相关的概念不谈，高层建筑里最为常用的结构体系便可分为如下几类： 1.抗弯矩框架。 2.支撑框架，包括偏心支撑框架。 3.剪力墙，包括钢板剪力墙。 4.筒中框架。 5.筒中筒结构。 6.核心交互结构。 7. 框格体系或束筒体系。 特别是由于最近趋向于更复杂的建筑形式，同时也需要增加刚度以抵抗几力和地震力，大多数高层建筑都具有由框架、支撑构架、剪力墙和相关体系相结合而构成的体系。而且，就较高的建筑物而言，大多数都是由交互式构件组成三维陈列。 将这些构件结合起来的方法正是高层建筑设计方法的本质。其结合方式需要在考虑环境、功能和费用后再发展，以便提供促使建筑发展达到新高度的有效结构。这并

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（ 二 〇 一 二 年 六 月 外文文献及翻译 题 目： About Buiding on the Structure Design 学生姓名： 学 院：土木工程学院 系 别：建筑工程系 专 业：土木工程(建筑工程方向) 班 级：土木08-4班 指导教师：

英文原文： Building construction concrete crack of prevention and processing Abstract The crack problem of concrete is a widespread existence but again difficult in solve of engineering actual problem, this text carried on a study analysis to a little bit familiar crack problem in the concrete engineering, and aim at concrete the circumstance put forward some prevention, processing measure. Keyword:Concrete crack prevention processing Foreword Concrete's ising 1 kind is anticipate by the freestone bone, cement, water and other mixture but formation of the in addition material of quality brittleness not and all material.Because the concrete construction transform with oneself, control etc. a series problem, harden model of in the concrete existence numerous tiny hole, spirit cave and tiny crack, is exactly because these beginning start blemish of existence just make the concrete present one some not and all the characteristic of quality.The tiny crack is a kind of harmless crack and accept concrete heavy, defend Shen and a little bit other use function not a creation to endanger.But after the concrete be subjected to lotus carry, difference in temperature etc. function, tiny crack would continuously of expand with connect, end formation we can see without the

单片机原理及应用课后习题参考答案~章

《单片机原理及应用》习题答案 第一章计算机基础知识 1-1 微型计算机主要由哪几部分组成？各部分有何功能？ 答：一台微型计算机由中央处理单元（CPU）、存储器、I/O接口及I/O设备等组成，相互之间通过三组总线（Bus）：即地址总线AB、数据总线DB和控制总线CB来连接。 CPU由运算器和控制器组成，运算器能够完成各种算术运算和逻辑运算操作，控制器用于控制计算机进行各种操作。 存储器是计算机系统中的“记忆”装置，其功能是存放程序和数据。按其功能可分为RAM和ROM。 输入/输出（I/O）接口是CPU与外部设备进行信息交换的部件。 总线是将CPU、存储器和I/O接口等相对独立的功能部件连接起来，并传送信息的公共通道。 1-3 什么叫单片机？其主要由哪几部分组成？ 答：单片机（Single Chip Microcomputer）是指把CPU、RAM、ROM、定时器/计数器以及I/O接口电路等主要部件集成在一块半导体芯片上的微型计算机。 1-4 在各种系列的单片机中，片内ROM的配置有几种形式？用户应根据什么原则来选用？ 答：单片机片内ROM的配置状态可分四种： （1）片内掩膜（Mask）ROM型单片机（如8051），适合于定型大批量应用产品的生产； （2）片内EPROM型单片机（如8751），适合于研制产品样机； （3）片内无ROM型单片机（如8031），需外接EPROM，单片机扩展灵活，适用于研制新产品；

（4）EEPROM（或Flash ROM）型单片机（如89C51），内部程序存储器电可擦除，使用更方便。 1-5 写出下列各数的另两种数制的表达形式（二、十、十六进制） 1-6 写出下列各数的BCD参与： 第二章MCS-51单片机的硬件结构 2-1 8052单片机片内包含哪些主要逻辑功能部件？ 答：8052单片机片内包括： ①8位中央处理器CPU一个 ②片内振荡器及时钟电路 ③256B数据存储器RAM。 ④8KB片内程序存储空间ROM ⑤21个特殊功能寄存器SFR ⑥4个8位并行I/O端口（32条线） ⑦1个可编程全双工串行口 ⑧可寻址64KB的外部程序存储空间和外部数据存储空间 ⑨3个16位的定时器/计数器

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学校 毕业设计（论文）附件 外文文献翻译 学号： xxxxx 姓名： xxx 所在系别： xxxxx 专业班级： xxx 指导教师： xxxx 原文标题： Building construction concrete crack of prevention and processing 2012年月日 .

建筑施工混凝土裂缝的预防与处理1 摘要 混凝土的裂缝问题是一个普遍存在而又难于解决的工程实际问题，本文对混凝土工程中常见的一些裂缝问题进行了探讨分析，并针对具体情况提出了一些预防、处理措施。 关键词：混凝土裂缝预防处理 前言 混凝土是一种由砂石骨料、水泥、水及其他外加材料混合而形成的非均质脆性材料。由于混凝土施工和本身变形、约束等一系列问题，硬化成型的混凝土中存在着众多的微孔隙、气穴和微裂缝，正是由于这些初始缺陷的存在才使混凝土呈现出一些非均质的特性。微裂缝通常是一种无害裂缝，对混凝土的承重、防渗及其他一些使用功能不产生危害。但是在混凝土受到荷载、温差等作用之后，微裂缝就会不断的扩展和连通，最终形成我们肉眼可见的宏观裂缝，也就是混凝土工程中常说的裂缝。 混凝土建筑和构件通常都是带缝工作的，由于裂缝的存在和发展通常会使内部的钢筋等材料产生腐蚀，降低钢筋混凝土材料的承载能力、耐久性及抗渗能力，影响建筑物的外观、使用寿命，严重者将会威胁到人们的生命和财产安全。很多工程的失事都是由于裂缝的不稳定发展所致。近代科学研究和大量的混凝土工程实践证明，在混凝土工程中裂缝问题是不可避免的，在一定的范围内也是可以接受的，只是要采取有效的措施将其危害程度控制在一定的范围之内。钢筋混凝土规范也明确规定：有些结构在所处的不同条件下，允许存在一定宽度的裂缝。但在施工中应尽量采取有效措施控制裂缝产生，使结构尽可能不出现裂缝或尽量减少裂缝的数量和宽度，尤其要尽量避免有害裂缝的出现，从而确保工程质量。 混凝土裂缝产生的原因很多，有变形引起的裂缝：如温度变化、收缩、膨胀、不均匀沉陷等原因引起的裂缝；有外载作用引起的裂缝；有养护环境不当和化学作用引起的裂缝等等。在实际工程中要区别对待，根据实际情况解决问题。 混凝土工程中常见裂缝及预防: 1.干缩裂缝及预防 干缩裂缝多出现在混凝土养护结束后的一段时间或是混凝土浇筑完毕后的一周左右。水泥浆中水分的蒸发会产生干缩，且这种收缩是不可逆的。干缩裂缝的产生主要是由于混凝土内外水分蒸发程度不同而导致变形不同的结果：混凝土受外部条件的影响，表面水分损失过快，变形较大，内部湿度变化较小变形较小，较大的表面干缩变形受到混凝土内部约束，产生较大拉应力而产生裂缝。相对湿度越低，水泥浆体干缩越大，干缩裂缝越易产 1原文出处及作者：《加拿大土木工程学报》

土木工程毕业设计外文翻译最终中英文

7 Rigid-Frame Structures A rigid-frame high-rise structure typically comprises parallel or orthogonally arranged bents consisting of columns and girders with moment resistant joints. Resistance to horizontal loading is provided by the bending resistance of the columns, girders, and joints. The continuity of the frame also contributes to resisting gravity loading, by reducing the moments in the girders. The advantages of a rigid frame are the simplicity and convenience of its rectangular form.Its unobstructed arrangement, clear of bracing members and structural walls, allows freedom internally for the layout and externally for the fenestration. Rig id frames are considered economical for buildings of up to' about 25 stories, above which their drift resistance is costly to control. If, however, a rigid frame is combined with shear walls or cores, the resulting structure is very much stiffer so that its height potential may extend up to 50 stories or more. A flat plate structure is very similar to a rigid frame, but with slabs replacing the girders As with a rigid frame, horizontal and vertical loadings are resisted in a flat plate structure by the flexural continuity between the vertical and horizontal components. As highly redundant structures, rigid frames are designed initially on the basis of approximate analyses, after which more rigorous analyses and checks can be made. The procedure may typically inc lude the following stages: 1. Estimation of gravity load forces in girders and columns by approximate method. 2. Preliminary estimate of member sizes based on gravity load forces with arbitrary increase in sizes to allow for horizontal loading. 3. Approximate allocation of horizontal loading to bents and preliminary analysis of member forces in bents. 4. Check on drift and adjustment of member sizes if necessary. 5. Check on strength of members for worst combination of gravity and horizontal loading, and adjustment of member sizes if necessary. 6. Computer analysis of total structure for more accurate check on member strengths and drift, with further adjustment of sizes where required. This stage may include the second-order P-Delta effects of gravity loading on the member forces and drift.. 7. Detailed design of members and connections.

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第1章单片机概述参考答案 1.1 答：微控制器，嵌入式控制器 1.2 答：CPU、存储器、I/O口、总线 1.3 答：C 1.4 答：B 1.5 答：微处理器、微处理机和CPU它们都是中央处理器的不同称谓，微处理器芯片本身不是计算机。而微计算机、单片机它们都是一个完整的计算机系统，单片机是集成在一个芯片上的用于测控目的的单片微计算机。 嵌入式处理器一般意义上讲，是指嵌入系统的单片机、DSP、嵌入式微处理器。目前多把嵌入式处理器多指嵌入式微处理器，例如ARM7、ARM9等。嵌入式微处理器相当于通用计算机中的CPU。与单片机相比，单片机本身（或稍加扩展）就是一个小的计算机系统，可独立运行，具有完整的功能。而嵌入式微处理器仅仅相当于单片机中的中央处理器。为了满足嵌入式应用的特殊要求，嵌入式微处理器虽然在功能上和标准微处理器基本是一样的，但在工作温度、抗电磁干扰、可靠性等方面一般都做了各种增强。 1.6 答：MCS-51系列单片机的基本型芯片分别：8031、8051和8071。它们的差别是在片内程序存储器上。8031无片内程序存储器、8051片内有4K字节的程序存储器ROM，而8751片内有集成有4K字节的程序存储器EPROM。 1.7 答：因为MCS-51系列单片机中的"MCS"是Intel公司生产的单片机的系列符号，而51系列单片机是指世界各个厂家生产的所有与8051的内核结构、指令系统兼容的单片机。 1.8 答：相当于MCS-51系列中的87C51，只不过是AT89S51芯片内的4K字节Flash存储器取代了87C51片内的4K字节的EPROM。 1.9 单片机体积小、价格低且易于掌握和普及，很容易嵌入到各种通用目的的系统中，实现各种方式的检测和控制。单片机在嵌入式处理器市场占有率最高，最大特点是价格低，体积小。 DSP是一种非常擅长于高速实现各种数字信号处理运算（如数字滤波、FFT、频谱分析等）的嵌入式处理器。由于对其硬件结构和指令进行了特殊设计，使其能够高速完成各种复杂的数字信号处理算法。广泛地用于通讯、网络通信、数字图像处理，电机控制系统，生物信息识别终端，实时语音压解系统等。这类智能化算法一般都是运算量较大，特别是向量运算、指针线性寻址等较多，而这些正是DSP的长处所在。与单片机相比，DSP具有的实现高速运算的硬件结构及指令和多总线，DSP处理的算法的复杂度和大的数据处理流量以及片内集成的多种功能部件更是单片机不可企及的。 嵌入式微处理器的基础是通用计算机中的CPU，它的地址总线数目较多能扩展较大的存储器空间，所以可配置实时多任务操作系统(RTOS)。RTOS是嵌入式应用软件的基础和开发平台。正由于嵌入式微处理器能运行实时多任务操作系统，所以能够处理复杂的系统管理任务和处理工作。因此，广泛地应用在移动计算平台、媒体手机、工业控制和商业领域（例如，智能工控设备、ATM机等）、电子商务平台、信息家电（机顶盒、数字电视）以及军事上的应用。 1.10 广义上讲，凡是系统中嵌入了"嵌入式处理器"，如单片机、DSP、嵌入式微处理器，都称其为"嵌入式系统"。但多数人把 "嵌入"嵌入式微处理器的系统，称为"嵌入式系统"。目前"嵌入式系统"还没有一个严格和权威的定义。目前人们所说的"嵌入式系统"，多指后者。 第2章 AT89S51单片机的硬件结构 1．答：AT89S51单片机的片内都集成了如下功能部件：（1）1个微处理器（CPU）；（2）128

土木工程外文翻译5

PROJECTCOSTCONTROL INTRODUCTION project a corporate image window and effectiveness of the source. With increasingly fierce market competition, the quality of work and the construction of civilizations rising material prices fluctuations. uncertainties and other factors, make the project operational in a relatively tough environment. So the cost of control is through the building of the project since the bidding phase of acceptance until the completion of the entire process, It is a comprehensive enterprise cost management an important part, we must organize and control measures in height to the attention with a view to improving the economic efficiency of enterprises to achieve the purpose. 2, outlining the construction project cost control, the cost of the project refers to the cost and process of formation occurred, on the production and operation of the amount of human resources, material resources and expenses, guidance, supervision, regulation and restrictions, in a timely manner to prevent, detect and correct errors in order to control costs in all project costs within the intended target. to guarantee the production and operation of enterprises benefits. 4, the construction cost control measures cost control measures. Reduce the cost of construction projects means, we should not only increase revenue is also reducing expenditure, or both also increase savings. Cutting expenditure is not only revenue, or revenue not only to cut expenditure, it is impossible to achieve the aim of reducing costs, at least there is no ideal lower cost effective.

土木工程毕业设计中英文翻译

附录：中英文翻译 英文部分： LOADS Loads that act on structures are usually classified as dead loads or live loads are fixed in location and constant in magnitude throughout the life of the the self-weight of a structure is the most important part of the structure and the unit weight of the density varies from about 90 to 120 pcf (14 to 19 KN/m)for lightweight concrete,and is about 145 pcf (23 KN/m)for normal calculating the dead load of structural concrete,usually a 5 pcf (1 KN/m)increment is included with the weight of the concrete to account for the presence of the reinforcement. Live loads are loads such as occupancy,snow,wind,or traffic loads,or seismic may be either fully or partially in place,or not present at may also change in location. Althought it is the responsibility of the engineer to calculate dead loads,live loads are usually specified by local,regional,or national codes and sources are the publications of the American National Standards Institute,the American Association of State Highway and Transportation Officials and,for wind loads,the recommendations of the ASCE Task Committee on Wind Forces. Specified live the loads usually include some allowance for overload,and may include measures such as posting of maximum loads will not be is oftern important to distinguish between the

单片机基础与应用习题答案第7章

1 第7章 串行口通信技术 参考答案 一、单选题 C B A D A C A A B B 二、填空题 1．并行通信、串行通信 2. 同步串行通信、异步串行通信 3. 起始位、数据位、校验位、停止位 4. 高，空闲位 5. 同步移位寄存器 6. TXD ，RXD 7. 时钟频率fosc ，时钟频率fosc 、PCON 中的SMOD 位 8. 1位起始位、8位数据位、1位停止位 9. 定时器T1的溢出率、SMOD 10. 进行电平转换 三、简答题 1. 并行通信速度快，传输线多，适合于近距离的数据通信，但硬件接线成本高；串行通信速度慢，但硬件成本低，传输线少，适合于长距离数据传输。 2．异步串行通信每次发送由起始位、数据位、校验位和停止位四部分构成的而一个字符帧，起始位：位于字符帧开头，只占一位，低电平，用于向接收设备表示发送端开始发送一帧信息。数据位：紧跟起始位之后的数据信息，低位在前，高位在后，用户可以自己定义数据位的长度。校验位：位于数据位之后，仅占一位，用来表征串行通信中采用奇校验还是偶校验，由用户编程决定。停止位：用来表征字符帧结束的位，高电平，通常可取1位、1.5位或2位。 3. 在方式1和方式3下，波特率由定时器T1的溢出率和SMOD 共同决定。即： 方式1和方式3的波特率=1T 32 2SMOD ?溢出率 当定时器/计数器T1做波特率发生器使用时，通常工作在模式2，即自动重装载的8位定时器，此时TL1作计数用，自动重装载的值在TH1内。设计数的预置值（初始值）为X ，那么每过256-X 个机器周期，定时器/计数器溢出一次，溢出周期为： )X 256(f 12osc -?。 溢出率为溢出周期的倒数，所以，波特率=) X 256(12f 322 osc SMOD -?。